clk: sunxi-ng: fix PLL_CPUX adjusting on H3
When adjusting PLL_CPUX on H3, the PLL is temporarily driven too high, and the system becomes unstable (oopses or hangs). Add a notifier to avoid this situation by temporarily switching to a known stable 24 MHz oscillator. Signed-off-by: Ondrej Jirman <megous@megous.com> Tested-by: Lutz Sammer <johns98@gmx.net> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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@ -803,6 +803,13 @@ static const struct sunxi_ccu_desc sun8i_h3_ccu_desc = {
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.num_resets = ARRAY_SIZE(sun8i_h3_ccu_resets),
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};
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static struct ccu_mux_nb sun8i_h3_cpu_nb = {
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.common = &cpux_clk.common,
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.cm = &cpux_clk.mux,
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.delay_us = 1, /* > 8 clock cycles at 24 MHz */
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.bypass_index = 1, /* index of 24 MHz oscillator */
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};
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static void __init sun8i_h3_ccu_setup(struct device_node *node)
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{
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void __iomem *reg;
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@ -821,6 +828,9 @@ static void __init sun8i_h3_ccu_setup(struct device_node *node)
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writel(val | (3 << 16), reg + SUN8I_H3_PLL_AUDIO_REG);
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sunxi_ccu_probe(node, reg, &sun8i_h3_ccu_desc);
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ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,
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&sun8i_h3_cpu_nb);
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}
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CLK_OF_DECLARE(sun8i_h3_ccu, "allwinner,sun8i-h3-ccu",
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sun8i_h3_ccu_setup);
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