usb: phy: samsung: remove old USB 2.0 PHY driver
drivers/usb/phy/phy-samsung-usb2 driver got replaced by drivers/phy/phy-samsung-usb2 one and is no longer used. Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Vivek Gautam <gautam.vivek@samsung.com> Reviewed-by: Jingoo Han <jg1.han@samsung.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com> Cc: Kamil Debski <k.debski@samsung.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
This commit is contained in:
Bartlomiej Zolnierkiewicz
Felipe Balbi
parent
fa31409a82
commit
a8b5b12eff
3 changed files with 0 additions and 550 deletions
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@ -78,14 +78,6 @@ config SAMSUNG_USBPHY
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This driver provides common interface to interact, for Samsung USB 2.0 PHY
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This driver provides common interface to interact, for Samsung USB 2.0 PHY
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driver and later for Samsung USB 3.0 PHY driver.
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driver and later for Samsung USB 3.0 PHY driver.
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config SAMSUNG_USB2PHY
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tristate "Samsung USB 2.0 PHY controller Driver"
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select SAMSUNG_USBPHY
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select USB_PHY
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help
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Enable this to support Samsung USB 2.0 (High Speed) PHY controller
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driver for Samsung SoCs.
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config SAMSUNG_USB3PHY
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config SAMSUNG_USB3PHY
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tristate "Samsung USB 3.0 PHY controller Driver"
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tristate "Samsung USB 3.0 PHY controller Driver"
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select SAMSUNG_USBPHY
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select SAMSUNG_USBPHY
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@ -15,7 +15,6 @@ obj-$(CONFIG_AM335X_CONTROL_USB) += phy-am335x-control.o
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obj-$(CONFIG_AM335X_PHY_USB) += phy-am335x.o
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obj-$(CONFIG_AM335X_PHY_USB) += phy-am335x.o
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obj-$(CONFIG_OMAP_OTG) += phy-omap-otg.o
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obj-$(CONFIG_OMAP_OTG) += phy-omap-otg.o
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obj-$(CONFIG_SAMSUNG_USBPHY) += phy-samsung-usb.o
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obj-$(CONFIG_SAMSUNG_USBPHY) += phy-samsung-usb.o
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obj-$(CONFIG_SAMSUNG_USB2PHY) += phy-samsung-usb2.o
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obj-$(CONFIG_SAMSUNG_USB3PHY) += phy-samsung-usb3.o
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obj-$(CONFIG_SAMSUNG_USB3PHY) += phy-samsung-usb3.o
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obj-$(CONFIG_TWL6030_USB) += phy-twl6030-usb.o
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obj-$(CONFIG_TWL6030_USB) += phy-twl6030-usb.o
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obj-$(CONFIG_USB_EHCI_TEGRA) += phy-tegra-usb.o
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obj-$(CONFIG_USB_EHCI_TEGRA) += phy-tegra-usb.o
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@ -1,541 +0,0 @@
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/* linux/drivers/usb/phy/phy-samsung-usb2.c
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*
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* Copyright (c) 2012 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Author: Praveen Paneri <p.paneri@samsung.com>
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*
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* Samsung USB2.0 PHY transceiver; talks to S3C HS OTG controller, EHCI-S5P and
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* OHCI-EXYNOS controllers.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/usb/otg.h>
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#include <linux/usb/samsung_usb_phy.h>
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#include <linux/platform_data/samsung-usbphy.h>
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#include "phy-samsung-usb.h"
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static int samsung_usbphy_set_host(struct usb_otg *otg, struct usb_bus *host)
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{
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if (!otg)
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return -ENODEV;
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if (!otg->host)
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otg->host = host;
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return 0;
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}
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static bool exynos5_phyhost_is_on(void __iomem *regs)
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{
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u32 reg;
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reg = readl(regs + EXYNOS5_PHY_HOST_CTRL0);
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return !(reg & HOST_CTRL0_SIDDQ);
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}
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static void samsung_exynos5_usb2phy_enable(struct samsung_usbphy *sphy)
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{
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void __iomem *regs = sphy->regs;
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u32 phyclk = sphy->ref_clk_freq;
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u32 phyhost;
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u32 phyotg;
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u32 phyhsic;
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u32 ehcictrl;
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u32 ohcictrl;
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/*
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* phy_usage helps in keeping usage count for phy
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* so that the first consumer enabling the phy is also
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* the last consumer to disable it.
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*/
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atomic_inc(&sphy->phy_usage);
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if (exynos5_phyhost_is_on(regs)) {
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dev_info(sphy->dev, "Already power on PHY\n");
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return;
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}
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/* Host configuration */
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phyhost = readl(regs + EXYNOS5_PHY_HOST_CTRL0);
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/* phy reference clock configuration */
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phyhost &= ~HOST_CTRL0_FSEL_MASK;
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phyhost |= HOST_CTRL0_FSEL(phyclk);
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/* host phy reset */
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phyhost &= ~(HOST_CTRL0_PHYSWRST |
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HOST_CTRL0_PHYSWRSTALL |
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HOST_CTRL0_SIDDQ |
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/* Enable normal mode of operation */
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HOST_CTRL0_FORCESUSPEND |
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HOST_CTRL0_FORCESLEEP);
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/* Link reset */
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phyhost |= (HOST_CTRL0_LINKSWRST |
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HOST_CTRL0_UTMISWRST |
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/* COMMON Block configuration during suspend */
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HOST_CTRL0_COMMONON_N);
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writel(phyhost, regs + EXYNOS5_PHY_HOST_CTRL0);
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udelay(10);
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phyhost &= ~(HOST_CTRL0_LINKSWRST |
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HOST_CTRL0_UTMISWRST);
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writel(phyhost, regs + EXYNOS5_PHY_HOST_CTRL0);
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/* OTG configuration */
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phyotg = readl(regs + EXYNOS5_PHY_OTG_SYS);
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/* phy reference clock configuration */
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phyotg &= ~OTG_SYS_FSEL_MASK;
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phyotg |= OTG_SYS_FSEL(phyclk);
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/* Enable normal mode of operation */
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phyotg &= ~(OTG_SYS_FORCESUSPEND |
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OTG_SYS_SIDDQ_UOTG |
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OTG_SYS_FORCESLEEP |
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OTG_SYS_REFCLKSEL_MASK |
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/* COMMON Block configuration during suspend */
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OTG_SYS_COMMON_ON);
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/* OTG phy & link reset */
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phyotg |= (OTG_SYS_PHY0_SWRST |
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OTG_SYS_LINKSWRST_UOTG |
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OTG_SYS_PHYLINK_SWRESET |
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OTG_SYS_OTGDISABLE |
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/* Set phy refclk */
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OTG_SYS_REFCLKSEL_CLKCORE);
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writel(phyotg, regs + EXYNOS5_PHY_OTG_SYS);
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udelay(10);
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phyotg &= ~(OTG_SYS_PHY0_SWRST |
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OTG_SYS_LINKSWRST_UOTG |
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OTG_SYS_PHYLINK_SWRESET);
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writel(phyotg, regs + EXYNOS5_PHY_OTG_SYS);
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/* HSIC phy configuration */
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phyhsic = (HSIC_CTRL_REFCLKDIV_12 |
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HSIC_CTRL_REFCLKSEL |
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HSIC_CTRL_PHYSWRST);
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writel(phyhsic, regs + EXYNOS5_PHY_HSIC_CTRL1);
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writel(phyhsic, regs + EXYNOS5_PHY_HSIC_CTRL2);
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udelay(10);
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phyhsic &= ~HSIC_CTRL_PHYSWRST;
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writel(phyhsic, regs + EXYNOS5_PHY_HSIC_CTRL1);
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writel(phyhsic, regs + EXYNOS5_PHY_HSIC_CTRL2);
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udelay(80);
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/* enable EHCI DMA burst */
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ehcictrl = readl(regs + EXYNOS5_PHY_HOST_EHCICTRL);
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ehcictrl |= (HOST_EHCICTRL_ENAINCRXALIGN |
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HOST_EHCICTRL_ENAINCR4 |
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HOST_EHCICTRL_ENAINCR8 |
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HOST_EHCICTRL_ENAINCR16);
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writel(ehcictrl, regs + EXYNOS5_PHY_HOST_EHCICTRL);
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/* set ohci_suspend_on_n */
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ohcictrl = readl(regs + EXYNOS5_PHY_HOST_OHCICTRL);
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ohcictrl |= HOST_OHCICTRL_SUSPLGCY;
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writel(ohcictrl, regs + EXYNOS5_PHY_HOST_OHCICTRL);
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}
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static void samsung_usb2phy_enable(struct samsung_usbphy *sphy)
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{
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void __iomem *regs = sphy->regs;
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u32 phypwr;
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u32 phyclk;
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u32 rstcon;
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/* set clock frequency for PLL */
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phyclk = sphy->ref_clk_freq;
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phypwr = readl(regs + SAMSUNG_PHYPWR);
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rstcon = readl(regs + SAMSUNG_RSTCON);
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switch (sphy->drv_data->cpu_type) {
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case TYPE_S3C64XX:
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phyclk &= ~PHYCLK_COMMON_ON_N;
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phypwr &= ~PHYPWR_NORMAL_MASK;
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rstcon |= RSTCON_SWRST;
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break;
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case TYPE_EXYNOS4X12:
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phypwr &= ~(PHYPWR_NORMAL_MASK_HSIC0 |
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PHYPWR_NORMAL_MASK_HSIC1 |
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PHYPWR_NORMAL_MASK_PHY1);
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rstcon |= RSTCON_HOSTPHY_SWRST;
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case TYPE_EXYNOS4210:
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phypwr &= ~PHYPWR_NORMAL_MASK_PHY0;
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rstcon |= RSTCON_SWRST;
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default:
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break;
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}
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writel(phyclk, regs + SAMSUNG_PHYCLK);
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/* Configure PHY0 for normal operation*/
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writel(phypwr, regs + SAMSUNG_PHYPWR);
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/* reset all ports of PHY and Link */
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writel(rstcon, regs + SAMSUNG_RSTCON);
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udelay(10);
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if (sphy->drv_data->cpu_type == TYPE_EXYNOS4X12)
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rstcon &= ~RSTCON_HOSTPHY_SWRST;
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rstcon &= ~RSTCON_SWRST;
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writel(rstcon, regs + SAMSUNG_RSTCON);
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}
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static void samsung_exynos5_usb2phy_disable(struct samsung_usbphy *sphy)
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{
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void __iomem *regs = sphy->regs;
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u32 phyhost;
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u32 phyotg;
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u32 phyhsic;
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if (atomic_dec_return(&sphy->phy_usage) > 0) {
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dev_info(sphy->dev, "still being used\n");
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return;
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}
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phyhsic = (HSIC_CTRL_REFCLKDIV_12 |
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HSIC_CTRL_REFCLKSEL |
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HSIC_CTRL_SIDDQ |
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HSIC_CTRL_FORCESLEEP |
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HSIC_CTRL_FORCESUSPEND);
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writel(phyhsic, regs + EXYNOS5_PHY_HSIC_CTRL1);
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writel(phyhsic, regs + EXYNOS5_PHY_HSIC_CTRL2);
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phyhost = readl(regs + EXYNOS5_PHY_HOST_CTRL0);
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phyhost |= (HOST_CTRL0_SIDDQ |
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HOST_CTRL0_FORCESUSPEND |
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HOST_CTRL0_FORCESLEEP |
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HOST_CTRL0_PHYSWRST |
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HOST_CTRL0_PHYSWRSTALL);
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writel(phyhost, regs + EXYNOS5_PHY_HOST_CTRL0);
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phyotg = readl(regs + EXYNOS5_PHY_OTG_SYS);
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phyotg |= (OTG_SYS_FORCESUSPEND |
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OTG_SYS_SIDDQ_UOTG |
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OTG_SYS_FORCESLEEP);
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writel(phyotg, regs + EXYNOS5_PHY_OTG_SYS);
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}
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static void samsung_usb2phy_disable(struct samsung_usbphy *sphy)
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{
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void __iomem *regs = sphy->regs;
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u32 phypwr;
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phypwr = readl(regs + SAMSUNG_PHYPWR);
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switch (sphy->drv_data->cpu_type) {
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case TYPE_S3C64XX:
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phypwr |= PHYPWR_NORMAL_MASK;
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break;
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case TYPE_EXYNOS4X12:
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phypwr |= (PHYPWR_NORMAL_MASK_HSIC0 |
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PHYPWR_NORMAL_MASK_HSIC1 |
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PHYPWR_NORMAL_MASK_PHY1);
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case TYPE_EXYNOS4210:
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phypwr |= PHYPWR_NORMAL_MASK_PHY0;
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default:
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break;
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}
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/* Disable analog and otg block power */
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writel(phypwr, regs + SAMSUNG_PHYPWR);
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}
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/*
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* The function passed to the usb driver for phy initialization
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*/
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static int samsung_usb2phy_init(struct usb_phy *phy)
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{
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struct samsung_usbphy *sphy;
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struct usb_bus *host = NULL;
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unsigned long flags;
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int ret = 0;
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sphy = phy_to_sphy(phy);
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host = phy->otg->host;
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/* Enable the phy clock */
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ret = clk_prepare_enable(sphy->clk);
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if (ret) {
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dev_err(sphy->dev, "%s: clk_prepare_enable failed\n", __func__);
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return ret;
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}
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spin_lock_irqsave(&sphy->lock, flags);
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if (host) {
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/* setting default phy-type for USB 2.0 */
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if (!strstr(dev_name(host->controller), "ehci") ||
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!strstr(dev_name(host->controller), "ohci"))
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samsung_usbphy_set_type(&sphy->phy, USB_PHY_TYPE_HOST);
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} else {
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samsung_usbphy_set_type(&sphy->phy, USB_PHY_TYPE_DEVICE);
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}
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/* Disable phy isolation */
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if (sphy->plat && sphy->plat->pmu_isolation)
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sphy->plat->pmu_isolation(false);
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else if (sphy->drv_data->set_isolation)
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sphy->drv_data->set_isolation(sphy, false);
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/* Selecting Host/OTG mode; After reset USB2.0PHY_CFG: HOST */
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samsung_usbphy_cfg_sel(sphy);
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/* Initialize usb phy registers */
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sphy->drv_data->phy_enable(sphy);
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spin_unlock_irqrestore(&sphy->lock, flags);
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/* Disable the phy clock */
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clk_disable_unprepare(sphy->clk);
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return ret;
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}
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/*
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* The function passed to the usb driver for phy shutdown
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*/
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|
||||||
static void samsung_usb2phy_shutdown(struct usb_phy *phy)
|
|
||||||
{
|
|
||||||
struct samsung_usbphy *sphy;
|
|
||||||
struct usb_bus *host = NULL;
|
|
||||||
unsigned long flags;
|
|
||||||
|
|
||||||
sphy = phy_to_sphy(phy);
|
|
||||||
|
|
||||||
host = phy->otg->host;
|
|
||||||
|
|
||||||
if (clk_prepare_enable(sphy->clk)) {
|
|
||||||
dev_err(sphy->dev, "%s: clk_prepare_enable failed\n", __func__);
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
spin_lock_irqsave(&sphy->lock, flags);
|
|
||||||
|
|
||||||
if (host) {
|
|
||||||
/* setting default phy-type for USB 2.0 */
|
|
||||||
if (!strstr(dev_name(host->controller), "ehci") ||
|
|
||||||
!strstr(dev_name(host->controller), "ohci"))
|
|
||||||
samsung_usbphy_set_type(&sphy->phy, USB_PHY_TYPE_HOST);
|
|
||||||
} else {
|
|
||||||
samsung_usbphy_set_type(&sphy->phy, USB_PHY_TYPE_DEVICE);
|
|
||||||
}
|
|
||||||
|
|
||||||
/* De-initialize usb phy registers */
|
|
||||||
sphy->drv_data->phy_disable(sphy);
|
|
||||||
|
|
||||||
/* Enable phy isolation */
|
|
||||||
if (sphy->plat && sphy->plat->pmu_isolation)
|
|
||||||
sphy->plat->pmu_isolation(true);
|
|
||||||
else if (sphy->drv_data->set_isolation)
|
|
||||||
sphy->drv_data->set_isolation(sphy, true);
|
|
||||||
|
|
||||||
spin_unlock_irqrestore(&sphy->lock, flags);
|
|
||||||
|
|
||||||
clk_disable_unprepare(sphy->clk);
|
|
||||||
}
|
|
||||||
|
|
||||||
static int samsung_usb2phy_probe(struct platform_device *pdev)
|
|
||||||
{
|
|
||||||
struct samsung_usbphy *sphy;
|
|
||||||
struct usb_otg *otg;
|
|
||||||
struct samsung_usbphy_data *pdata = dev_get_platdata(&pdev->dev);
|
|
||||||
const struct samsung_usbphy_drvdata *drv_data;
|
|
||||||
struct device *dev = &pdev->dev;
|
|
||||||
struct resource *phy_mem;
|
|
||||||
void __iomem *phy_base;
|
|
||||||
struct clk *clk;
|
|
||||||
int ret;
|
|
||||||
|
|
||||||
phy_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
||||||
phy_base = devm_ioremap_resource(dev, phy_mem);
|
|
||||||
if (IS_ERR(phy_base))
|
|
||||||
return PTR_ERR(phy_base);
|
|
||||||
|
|
||||||
sphy = devm_kzalloc(dev, sizeof(*sphy), GFP_KERNEL);
|
|
||||||
if (!sphy)
|
|
||||||
return -ENOMEM;
|
|
||||||
|
|
||||||
otg = devm_kzalloc(dev, sizeof(*otg), GFP_KERNEL);
|
|
||||||
if (!otg)
|
|
||||||
return -ENOMEM;
|
|
||||||
|
|
||||||
drv_data = samsung_usbphy_get_driver_data(pdev);
|
|
||||||
|
|
||||||
if (drv_data->cpu_type == TYPE_EXYNOS5250)
|
|
||||||
clk = devm_clk_get(dev, "usbhost");
|
|
||||||
else
|
|
||||||
clk = devm_clk_get(dev, "otg");
|
|
||||||
|
|
||||||
if (IS_ERR(clk)) {
|
|
||||||
dev_err(dev, "Failed to get usbhost/otg clock\n");
|
|
||||||
return PTR_ERR(clk);
|
|
||||||
}
|
|
||||||
|
|
||||||
sphy->dev = dev;
|
|
||||||
|
|
||||||
if (dev->of_node) {
|
|
||||||
ret = samsung_usbphy_parse_dt(sphy);
|
|
||||||
if (ret < 0)
|
|
||||||
return ret;
|
|
||||||
} else {
|
|
||||||
if (!pdata) {
|
|
||||||
dev_err(dev, "no platform data specified\n");
|
|
||||||
return -EINVAL;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
sphy->plat = pdata;
|
|
||||||
sphy->regs = phy_base;
|
|
||||||
sphy->clk = clk;
|
|
||||||
sphy->drv_data = drv_data;
|
|
||||||
sphy->phy.dev = sphy->dev;
|
|
||||||
sphy->phy.label = "samsung-usb2phy";
|
|
||||||
sphy->phy.type = USB_PHY_TYPE_USB2;
|
|
||||||
sphy->phy.init = samsung_usb2phy_init;
|
|
||||||
sphy->phy.shutdown = samsung_usb2phy_shutdown;
|
|
||||||
|
|
||||||
sphy->ref_clk_freq = samsung_usbphy_get_refclk_freq(sphy);
|
|
||||||
if (sphy->ref_clk_freq < 0)
|
|
||||||
return -EINVAL;
|
|
||||||
|
|
||||||
sphy->phy.otg = otg;
|
|
||||||
sphy->phy.otg->phy = &sphy->phy;
|
|
||||||
sphy->phy.otg->set_host = samsung_usbphy_set_host;
|
|
||||||
|
|
||||||
spin_lock_init(&sphy->lock);
|
|
||||||
|
|
||||||
platform_set_drvdata(pdev, sphy);
|
|
||||||
|
|
||||||
return usb_add_phy_dev(&sphy->phy);
|
|
||||||
}
|
|
||||||
|
|
||||||
static int samsung_usb2phy_remove(struct platform_device *pdev)
|
|
||||||
{
|
|
||||||
struct samsung_usbphy *sphy = platform_get_drvdata(pdev);
|
|
||||||
|
|
||||||
usb_remove_phy(&sphy->phy);
|
|
||||||
|
|
||||||
if (sphy->pmuregs)
|
|
||||||
iounmap(sphy->pmuregs);
|
|
||||||
if (sphy->sysreg)
|
|
||||||
iounmap(sphy->sysreg);
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
static const struct samsung_usbphy_drvdata usb2phy_s3c64xx = {
|
|
||||||
.cpu_type = TYPE_S3C64XX,
|
|
||||||
.devphy_en_mask = S3C64XX_USBPHY_ENABLE,
|
|
||||||
.rate_to_clksel = samsung_usbphy_rate_to_clksel_64xx,
|
|
||||||
.set_isolation = NULL, /* TODO */
|
|
||||||
.phy_enable = samsung_usb2phy_enable,
|
|
||||||
.phy_disable = samsung_usb2phy_disable,
|
|
||||||
};
|
|
||||||
|
|
||||||
static const struct samsung_usbphy_drvdata usb2phy_exynos4 = {
|
|
||||||
.cpu_type = TYPE_EXYNOS4210,
|
|
||||||
.devphy_en_mask = EXYNOS_USBPHY_ENABLE,
|
|
||||||
.hostphy_en_mask = EXYNOS_USBPHY_ENABLE,
|
|
||||||
.rate_to_clksel = samsung_usbphy_rate_to_clksel_64xx,
|
|
||||||
.set_isolation = samsung_usbphy_set_isolation_4210,
|
|
||||||
.phy_enable = samsung_usb2phy_enable,
|
|
||||||
.phy_disable = samsung_usb2phy_disable,
|
|
||||||
};
|
|
||||||
|
|
||||||
static const struct samsung_usbphy_drvdata usb2phy_exynos4x12 = {
|
|
||||||
.cpu_type = TYPE_EXYNOS4X12,
|
|
||||||
.devphy_en_mask = EXYNOS_USBPHY_ENABLE,
|
|
||||||
.hostphy_en_mask = EXYNOS_USBPHY_ENABLE,
|
|
||||||
.rate_to_clksel = samsung_usbphy_rate_to_clksel_4x12,
|
|
||||||
.set_isolation = samsung_usbphy_set_isolation_4210,
|
|
||||||
.phy_enable = samsung_usb2phy_enable,
|
|
||||||
.phy_disable = samsung_usb2phy_disable,
|
|
||||||
};
|
|
||||||
|
|
||||||
static struct samsung_usbphy_drvdata usb2phy_exynos5 = {
|
|
||||||
.cpu_type = TYPE_EXYNOS5250,
|
|
||||||
.hostphy_en_mask = EXYNOS_USBPHY_ENABLE,
|
|
||||||
.hostphy_reg_offset = EXYNOS_USBHOST_PHY_CTRL_OFFSET,
|
|
||||||
.rate_to_clksel = samsung_usbphy_rate_to_clksel_4x12,
|
|
||||||
.set_isolation = samsung_usbphy_set_isolation_4210,
|
|
||||||
.phy_enable = samsung_exynos5_usb2phy_enable,
|
|
||||||
.phy_disable = samsung_exynos5_usb2phy_disable,
|
|
||||||
};
|
|
||||||
|
|
||||||
#ifdef CONFIG_OF
|
|
||||||
static const struct of_device_id samsung_usbphy_dt_match[] = {
|
|
||||||
{
|
|
||||||
.compatible = "samsung,s3c64xx-usb2phy",
|
|
||||||
.data = &usb2phy_s3c64xx,
|
|
||||||
}, {
|
|
||||||
.compatible = "samsung,exynos4210-usb2phy",
|
|
||||||
.data = &usb2phy_exynos4,
|
|
||||||
}, {
|
|
||||||
.compatible = "samsung,exynos4x12-usb2phy",
|
|
||||||
.data = &usb2phy_exynos4x12,
|
|
||||||
}, {
|
|
||||||
.compatible = "samsung,exynos5250-usb2phy",
|
|
||||||
.data = &usb2phy_exynos5
|
|
||||||
},
|
|
||||||
{},
|
|
||||||
};
|
|
||||||
MODULE_DEVICE_TABLE(of, samsung_usbphy_dt_match);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
static struct platform_device_id samsung_usbphy_driver_ids[] = {
|
|
||||||
{
|
|
||||||
.name = "s3c64xx-usb2phy",
|
|
||||||
.driver_data = (unsigned long)&usb2phy_s3c64xx,
|
|
||||||
}, {
|
|
||||||
.name = "exynos4210-usb2phy",
|
|
||||||
.driver_data = (unsigned long)&usb2phy_exynos4,
|
|
||||||
}, {
|
|
||||||
.name = "exynos4x12-usb2phy",
|
|
||||||
.driver_data = (unsigned long)&usb2phy_exynos4x12,
|
|
||||||
}, {
|
|
||||||
.name = "exynos5250-usb2phy",
|
|
||||||
.driver_data = (unsigned long)&usb2phy_exynos5,
|
|
||||||
},
|
|
||||||
{},
|
|
||||||
};
|
|
||||||
|
|
||||||
MODULE_DEVICE_TABLE(platform, samsung_usbphy_driver_ids);
|
|
||||||
|
|
||||||
static struct platform_driver samsung_usb2phy_driver = {
|
|
||||||
.probe = samsung_usb2phy_probe,
|
|
||||||
.remove = samsung_usb2phy_remove,
|
|
||||||
.id_table = samsung_usbphy_driver_ids,
|
|
||||||
.driver = {
|
|
||||||
.name = "samsung-usb2phy",
|
|
||||||
.owner = THIS_MODULE,
|
|
||||||
.of_match_table = of_match_ptr(samsung_usbphy_dt_match),
|
|
||||||
},
|
|
||||||
};
|
|
||||||
|
|
||||||
module_platform_driver(samsung_usb2phy_driver);
|
|
||||||
|
|
||||||
MODULE_DESCRIPTION("Samsung USB 2.0 phy controller");
|
|
||||||
MODULE_AUTHOR("Praveen Paneri <p.paneri@samsung.com>");
|
|
||||||
MODULE_LICENSE("GPL");
|
|
||||||
MODULE_ALIAS("platform:samsung-usb2phy");
|
|
||||||
Loading…
Reference in a new issue