perf, x86: Improve the PEBS ABI
Rename perf_event_attr::precise to perf_event_attr::precise_ip and widen it to 2 bits. This new field describes the required precision of the PERF_SAMPLE_IP field: 0 - SAMPLE_IP can have arbitrary skid 1 - SAMPLE_IP must have constant skid 2 - SAMPLE_IP requested to have 0 skid 3 - SAMPLE_IP must have 0 skid And modify the Intel PEBS code accordingly. The PEBS implementation now supports up to precise_ip == 2, where we perform the IP fixup. Also s/PERF_RECORD_MISC_EXACT/&_IP/ to clarify its meaning, this bit should be set for each PERF_SAMPLE_IP field known to match the actual instruction triggering the event. This new scheme allows for a PEBS mode that uses the buffer for more than a single event. Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Paul Mackerras <paulus@samba.org> Cc: Stephane Eranian <eranian@google.com> LKML-Reference: <new-submission> Signed-off-by: Ingo Molnar <mingo@elte.hu>
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6 changed files with 59 additions and 22 deletions
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@ -488,6 +488,21 @@ static int x86_setup_perfctr(struct perf_event *event)
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static int x86_pmu_hw_config(struct perf_event *event)
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{
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if (event->attr.precise_ip) {
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int precise = 0;
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/* Support for constant skid */
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if (x86_pmu.pebs)
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precise++;
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/* Support for IP fixup */
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if (x86_pmu.lbr_nr)
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precise++;
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if (event->attr.precise_ip > precise)
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return -EOPNOTSUPP;
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}
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/*
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* Generate PMC IRQs:
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* (keep 'enabled' bit clear for now)
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@ -1780,7 +1795,7 @@ unsigned long perf_misc_flags(struct pt_regs *regs)
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}
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if (regs->flags & PERF_EFLAGS_EXACT)
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misc |= PERF_RECORD_MISC_EXACT;
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misc |= PERF_RECORD_MISC_EXACT_IP;
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return misc;
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}
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@ -563,7 +563,7 @@ static void intel_pmu_disable_event(struct perf_event *event)
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x86_pmu_disable_event(event);
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if (unlikely(event->attr.precise))
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if (unlikely(event->attr.precise_ip))
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intel_pmu_pebs_disable(event);
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}
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@ -615,7 +615,7 @@ static void intel_pmu_enable_event(struct perf_event *event)
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return;
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}
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if (unlikely(event->attr.precise))
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if (unlikely(event->attr.precise_ip))
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intel_pmu_pebs_enable(event);
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__x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
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@ -307,7 +307,7 @@ intel_pebs_constraints(struct perf_event *event)
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{
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struct event_constraint *c;
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if (!event->attr.precise)
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if (!event->attr.precise_ip)
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return NULL;
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if (x86_pmu.pebs_constraints) {
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@ -330,7 +330,7 @@ static void intel_pmu_pebs_enable(struct perf_event *event)
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cpuc->pebs_enabled |= 1ULL << hwc->idx;
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WARN_ON_ONCE(cpuc->enabled);
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if (x86_pmu.intel_cap.pebs_trap)
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if (x86_pmu.intel_cap.pebs_trap && event->attr.precise_ip > 1)
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intel_pmu_lbr_enable(event);
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}
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@ -345,7 +345,7 @@ static void intel_pmu_pebs_disable(struct perf_event *event)
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hwc->config |= ARCH_PERFMON_EVENTSEL_INT;
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if (x86_pmu.intel_cap.pebs_trap)
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if (x86_pmu.intel_cap.pebs_trap && event->attr.precise_ip > 1)
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intel_pmu_lbr_disable(event);
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}
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@ -485,7 +485,7 @@ static void __intel_pmu_pebs_event(struct perf_event *event,
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regs.bp = pebs->bp;
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regs.sp = pebs->sp;
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if (intel_pmu_pebs_fixup_ip(regs))
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if (event->attr.precise_ip > 1 && intel_pmu_pebs_fixup_ip(®s))
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regs.flags |= PERF_EFLAGS_EXACT;
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else
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regs.flags &= ~PERF_EFLAGS_EXACT;
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@ -518,7 +518,7 @@ static void intel_pmu_drain_pebs_core(struct pt_regs *iregs)
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WARN_ON_ONCE(!event);
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if (!event->attr.precise)
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if (!event->attr.precise_ip)
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return;
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n = top - at;
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@ -570,7 +570,7 @@ static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs)
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WARN_ON_ONCE(!event);
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if (!event->attr.precise)
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if (!event->attr.precise_ip)
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continue;
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if (__test_and_set_bit(bit, (unsigned long *)&status))
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@ -203,9 +203,19 @@ struct perf_event_attr {
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enable_on_exec : 1, /* next exec enables */
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task : 1, /* trace fork/exit */
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watermark : 1, /* wakeup_watermark */
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precise : 1, /* OoO invariant counter */
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/*
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* precise_ip:
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*
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* 0 - SAMPLE_IP can have arbitrary skid
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* 1 - SAMPLE_IP must have constant skid
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* 2 - SAMPLE_IP requested to have 0 skid
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* 3 - SAMPLE_IP must have 0 skid
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*
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* See also PERF_RECORD_MISC_EXACT_IP
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*/
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precise_ip : 2, /* skid constraint */
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__reserved_1 : 48;
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__reserved_1 : 47;
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union {
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__u32 wakeup_events; /* wakeup every n events */
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@ -296,7 +306,12 @@ struct perf_event_mmap_page {
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#define PERF_RECORD_MISC_GUEST_KERNEL (4 << 0)
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#define PERF_RECORD_MISC_GUEST_USER (5 << 0)
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#define PERF_RECORD_MISC_EXACT (1 << 14)
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/*
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* Indicates that the content of PERF_SAMPLE_IP points to
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* the actual instruction that triggered the event. See also
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* perf_event_attr::precise_ip.
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*/
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#define PERF_RECORD_MISC_EXACT_IP (1 << 14)
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/*
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* Reserve the last bit to indicate some extended misc field
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*/
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@ -1021,7 +1021,7 @@ static void event__process_sample(const event_t *self,
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return;
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}
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if (self->header.misc & PERF_RECORD_MISC_EXACT)
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if (self->header.misc & PERF_RECORD_MISC_EXACT_IP)
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exact_samples++;
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if (event__preprocess_sample(self, session, &al, symbol_filter) < 0 ||
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@ -654,10 +654,6 @@ parse_raw_event(const char **strp, struct perf_event_attr *attr)
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return EVT_FAILED;
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n = hex2u64(str + 1, &config);
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if (n > 0) {
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if (str[n+1] == 'p') {
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attr->precise = 1;
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n++;
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}
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*strp = str + n + 1;
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attr->type = PERF_TYPE_RAW;
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attr->config = config;
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@ -692,19 +688,29 @@ static enum event_result
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parse_event_modifier(const char **strp, struct perf_event_attr *attr)
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{
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const char *str = *strp;
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int eu = 1, ek = 1, eh = 1;
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int exclude = 0;
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int eu = 0, ek = 0, eh = 0, precise = 0;
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if (*str++ != ':')
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return 0;
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while (*str) {
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if (*str == 'u')
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if (*str == 'u') {
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if (!exclude)
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exclude = eu = ek = eh = 1;
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eu = 0;
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else if (*str == 'k')
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} else if (*str == 'k') {
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if (!exclude)
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exclude = eu = ek = eh = 1;
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ek = 0;
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else if (*str == 'h')
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} else if (*str == 'h') {
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if (!exclude)
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exclude = eu = ek = eh = 1;
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eh = 0;
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else
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} else if (*str == 'p') {
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precise++;
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} else
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break;
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++str;
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}
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if (str >= *strp + 2) {
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@ -712,6 +718,7 @@ parse_event_modifier(const char **strp, struct perf_event_attr *attr)
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attr->exclude_user = eu;
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attr->exclude_kernel = ek;
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attr->exclude_hv = eh;
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attr->precise_ip = precise;
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return 1;
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}
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return 0;
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