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drm/amdgpu/display: remove VEGA20 config option

Browse source 
Leftover from bringup.  No need to keep it around for
upstream.

Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher 2018-05-16 15:28:59 -05:00
parent 2b6dc93a3d
commit b4b9f944e4
5 changed files with 0 additions and 195 deletions
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8
drivers/gpu/drm/amd/display/Kconfig
View file

@ -34,12 +34,4 @@ config DEBUG_KERNEL_DC
if you want to hit if you want to hit
kdgb_break in assert. kdgb_break in assert.
config DRM_AMD_DC_VG20
bool "Vega20 support"
depends on DRM_AMD_DC
help
Choose this option if you want to have
Vega20 support for display engine
endmenu endmenu

2
drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
View file

@ -1331,9 +1331,7 @@ static enum bp_result bios_parser_get_firmware_info(
result = get_firmware_info_v3_2(bp, info); result = get_firmware_info_v3_2(bp, info);
break; break;
case 3: case 3:
#ifdef CONFIG_DRM_AMD_DC_VG20
result = get_firmware_info_v3_2(bp, info); result = get_firmware_info_v3_2(bp, info);
#endif
break; break;
default: default:
break; break;

6
drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
View file

@ -413,18 +413,12 @@ static int dce112_set_clock(
/*VBIOS will determine DPREFCLK frequency, so we don't set it*/ /*VBIOS will determine DPREFCLK frequency, so we don't set it*/
dce_clk_params.target_clock_frequency = 0; dce_clk_params.target_clock_frequency = 0;
dce_clk_params.clock_type = DCECLOCK_TYPE_DPREFCLK; dce_clk_params.clock_type = DCECLOCK_TYPE_DPREFCLK;
#ifndef CONFIG_DRM_AMD_DC_VG20
dce_clk_params.flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK =
(dce_clk_params.pll_id ==
CLOCK_SOURCE_COMBO_DISPLAY_PLL0);
#else
if (!ASICREV_IS_VEGA20_P(clk->ctx->asic_id.hw_internal_rev)) if (!ASICREV_IS_VEGA20_P(clk->ctx->asic_id.hw_internal_rev))
dce_clk_params.flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK = dce_clk_params.flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK =
(dce_clk_params.pll_id == (dce_clk_params.pll_id ==
CLOCK_SOURCE_COMBO_DISPLAY_PLL0); CLOCK_SOURCE_COMBO_DISPLAY_PLL0);
else else
dce_clk_params.flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK = false; dce_clk_params.flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK = false;
#endif
bp->funcs->set_dce_clock(bp, &dce_clk_params); bp->funcs->set_dce_clock(bp, &dce_clk_params);

177
drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
View file

@ -814,7 +814,6 @@ static void bw_calcs_data_update_from_pplib(struct dc *dc)
dm_pp_notify_wm_clock_changes(dc->ctx, &clk_ranges); dm_pp_notify_wm_clock_changes(dc->ctx, &clk_ranges);
} }
#ifdef CONFIG_DRM_AMD_DC_VG20
static uint32_t read_pipe_fuses(struct dc_context *ctx) static uint32_t read_pipe_fuses(struct dc_context *ctx)
{ {
uint32_t value = dm_read_reg_soc15(ctx, mmCC_DC_PIPE_DIS, 0); uint32_t value = dm_read_reg_soc15(ctx, mmCC_DC_PIPE_DIS, 0);
@ -1020,182 +1019,6 @@ res_create_fail:
return false; return false;
} }
#else
static bool construct(
uint8_t num_virtual_links,
struct dc *dc,
struct dce110_resource_pool *pool)
{
unsigned int i;
struct dc_context *ctx = dc->ctx;
struct irq_service_init_data irq_init_data;
ctx->dc_bios->regs = &bios_regs;
pool->base.res_cap = &res_cap;
pool->base.funcs = &dce120_res_pool_funcs;
/* TODO: Fill more data from GreenlandAsicCapability.cpp */
pool->base.pipe_count = res_cap.num_timing_generator;
pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator;
pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
dc->caps.max_downscale_ratio = 200;
dc->caps.i2c_speed_in_khz = 100;
dc->caps.max_cursor_size = 128;
dc->caps.dual_link_dvi = true;
dc->debug = debug_defaults;
/*************************************************
* Create resources *
*************************************************/
pool->base.clock_sources[DCE120_CLK_SRC_PLL0] =
dce120_clock_source_create(ctx, ctx->dc_bios,
CLOCK_SOURCE_COMBO_PHY_PLL0,
&clk_src_regs[0], false);
pool->base.clock_sources[DCE120_CLK_SRC_PLL1] =
dce120_clock_source_create(ctx, ctx->dc_bios,
CLOCK_SOURCE_COMBO_PHY_PLL1,
&clk_src_regs[1], false);
pool->base.clock_sources[DCE120_CLK_SRC_PLL2] =
dce120_clock_source_create(ctx, ctx->dc_bios,
CLOCK_SOURCE_COMBO_PHY_PLL2,
&clk_src_regs[2], false);
pool->base.clock_sources[DCE120_CLK_SRC_PLL3] =
dce120_clock_source_create(ctx, ctx->dc_bios,
CLOCK_SOURCE_COMBO_PHY_PLL3,
&clk_src_regs[3], false);
pool->base.clock_sources[DCE120_CLK_SRC_PLL4] =
dce120_clock_source_create(ctx, ctx->dc_bios,
CLOCK_SOURCE_COMBO_PHY_PLL4,
&clk_src_regs[4], false);
pool->base.clock_sources[DCE120_CLK_SRC_PLL5] =
dce120_clock_source_create(ctx, ctx->dc_bios,
CLOCK_SOURCE_COMBO_PHY_PLL5,
&clk_src_regs[5], false);
pool->base.clk_src_count = DCE120_CLK_SRC_TOTAL;
pool->base.dp_clock_source =
dce120_clock_source_create(ctx, ctx->dc_bios,
CLOCK_SOURCE_ID_DP_DTO,
&clk_src_regs[0], true);
for (i = 0; i < pool->base.clk_src_count; i++) {
if (pool->base.clock_sources[i] == NULL) {
dm_error("DC: failed to create clock sources!\n");
BREAK_TO_DEBUGGER();
goto clk_src_create_fail;
}
}
pool->base.display_clock = dce120_disp_clk_create(ctx);
if (pool->base.display_clock == NULL) {
dm_error("DC: failed to create display clock!\n");
BREAK_TO_DEBUGGER();
goto disp_clk_create_fail;
}
pool->base.dmcu = dce_dmcu_create(ctx,
&dmcu_regs,
&dmcu_shift,
&dmcu_mask);
if (pool->base.dmcu == NULL) {
dm_error("DC: failed to create dmcu!\n");
BREAK_TO_DEBUGGER();
goto res_create_fail;
}
pool->base.abm = dce_abm_create(ctx,
&abm_regs,
&abm_shift,
&abm_mask);
if (pool->base.abm == NULL) {
dm_error("DC: failed to create abm!\n");
BREAK_TO_DEBUGGER();
goto res_create_fail;
}
irq_init_data.ctx = dc->ctx;
pool->base.irqs = dal_irq_service_dce120_create(&irq_init_data);
if (!pool->base.irqs)
goto irqs_create_fail;
for (i = 0; i < pool->base.pipe_count; i++) {
pool->base.timing_generators[i] =
dce120_timing_generator_create(
ctx,
i,
&dce120_tg_offsets[i]);
if (pool->base.timing_generators[i] == NULL) {
BREAK_TO_DEBUGGER();
dm_error("DC: failed to create tg!\n");
goto controller_create_fail;
}
pool->base.mis[i] = dce120_mem_input_create(ctx, i);
if (pool->base.mis[i] == NULL) {
BREAK_TO_DEBUGGER();
dm_error(
"DC: failed to create memory input!\n");
goto controller_create_fail;
}
pool->base.ipps[i] = dce120_ipp_create(ctx, i);
if (pool->base.ipps[i] == NULL) {
BREAK_TO_DEBUGGER();
dm_error(
"DC: failed to create input pixel processor!\n");
goto controller_create_fail;
}
pool->base.transforms[i] = dce120_transform_create(ctx, i);
if (pool->base.transforms[i] == NULL) {
BREAK_TO_DEBUGGER();
dm_error(
"DC: failed to create transform!\n");
goto res_create_fail;
}
pool->base.opps[i] = dce120_opp_create(
ctx,
i);
if (pool->base.opps[i] == NULL) {
BREAK_TO_DEBUGGER();
dm_error(
"DC: failed to create output pixel processor!\n");
}
}
if (!resource_construct(num_virtual_links, dc, &pool->base,
&res_create_funcs))
goto res_create_fail;
/* Create hardware sequencer */
if (!dce120_hw_sequencer_create(dc))
goto controller_create_fail;
dc->caps.max_planes = pool->base.pipe_count;
bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id);
bw_calcs_data_update_from_pplib(dc);
return true;
irqs_create_fail:
controller_create_fail:
disp_clk_create_fail:
clk_src_create_fail:
res_create_fail:
destruct(pool);
return false;
}
#endif
struct resource_pool *dce120_create_resource_pool( struct resource_pool *dce120_create_resource_pool(
uint8_t num_virtual_links, uint8_t num_virtual_links,

2
drivers/gpu/drm/amd/display/include/dal_asic_id.h
View file

@ -115,10 +115,8 @@
/* DCE12 */ /* DCE12 */
#define AI_UNKNOWN 0xFF #define AI_UNKNOWN 0xFF
#ifdef CONFIG_DRM_AMD_DC_VG20
#define AI_VEGA20_P_A0 40 #define AI_VEGA20_P_A0 40
#define ASICREV_IS_VEGA20_P(eChipRev) ((eChipRev >= AI_VEGA20_P_A0) && (eChipRev < AI_UNKNOWN)) #define ASICREV_IS_VEGA20_P(eChipRev) ((eChipRev >= AI_VEGA20_P_A0) && (eChipRev < AI_UNKNOWN))
#endif
#define AI_GREENLAND_P_A0 1 #define AI_GREENLAND_P_A0 1
#define AI_GREENLAND_P_A1 2 #define AI_GREENLAND_P_A1 2