Merge branch 'for-linus' into next
Conflicts: drivers/dma/edma.c Moved the memory leak fix post merge Signed-off-by: Vinod Koul <vinod.koul@intel.com>
This commit is contained in:
Vinod Koul
commit
b967aecf17
12 changed files with 254 additions and 135 deletions
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@ -28,7 +28,7 @@ The three cells in order are:
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dependent:
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- bit 7-0: peripheral identifier for the hardware handshaking interface. The
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identifier can be different for tx and rx.
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- bit 11-8: FIFO configuration. 0 for half FIFO, 1 for ALAP, 1 for ASAP.
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- bit 11-8: FIFO configuration. 0 for half FIFO, 1 for ALAP, 2 for ASAP.
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Example:
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@ -2133,8 +2133,7 @@ static int pl08x_probe(struct amba_device *adev, const struct amba_id *id)
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writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR);
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writel(0x000000FF, pl08x->base + PL080_TC_CLEAR);
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ret = request_irq(adev->irq[0], pl08x_irq, IRQF_DISABLED,
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DRIVER_NAME, pl08x);
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ret = request_irq(adev->irq[0], pl08x_irq, 0, DRIVER_NAME, pl08x);
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if (ret) {
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dev_err(&adev->dev, "%s failed to request interrupt %d\n",
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__func__, adev->irq[0]);
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@ -2694,7 +2694,7 @@ static int __init coh901318_probe(struct platform_device *pdev)
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if (irq < 0)
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return irq;
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err = devm_request_irq(&pdev->dev, irq, dma_irq_handler, IRQF_DISABLED,
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err = devm_request_irq(&pdev->dev, irq, dma_irq_handler, 0,
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"coh901318", base);
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if (err)
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return err;
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@ -674,14 +674,14 @@ static void cleanup_chans(struct cppi41_dd *cdd)
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}
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}
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static int cppi41_add_chans(struct platform_device *pdev, struct cppi41_dd *cdd)
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static int cppi41_add_chans(struct device *dev, struct cppi41_dd *cdd)
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{
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struct cppi41_channel *cchan;
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int i;
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int ret;
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u32 n_chans;
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ret = of_property_read_u32(pdev->dev.of_node, "#dma-channels",
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ret = of_property_read_u32(dev->of_node, "#dma-channels",
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&n_chans);
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if (ret)
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return ret;
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@ -719,7 +719,7 @@ err:
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return -ENOMEM;
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}
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static void purge_descs(struct platform_device *pdev, struct cppi41_dd *cdd)
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static void purge_descs(struct device *dev, struct cppi41_dd *cdd)
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{
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unsigned int mem_decs;
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int i;
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@ -731,7 +731,7 @@ static void purge_descs(struct platform_device *pdev, struct cppi41_dd *cdd)
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cppi_writel(0, cdd->qmgr_mem + QMGR_MEMBASE(i));
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cppi_writel(0, cdd->qmgr_mem + QMGR_MEMCTRL(i));
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dma_free_coherent(&pdev->dev, mem_decs, cdd->cd,
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dma_free_coherent(dev, mem_decs, cdd->cd,
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cdd->descs_phys);
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}
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}
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@ -741,19 +741,19 @@ static void disable_sched(struct cppi41_dd *cdd)
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cppi_writel(0, cdd->sched_mem + DMA_SCHED_CTRL);
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}
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static void deinit_cpii41(struct platform_device *pdev, struct cppi41_dd *cdd)
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static void deinit_cppi41(struct device *dev, struct cppi41_dd *cdd)
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{
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disable_sched(cdd);
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purge_descs(pdev, cdd);
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purge_descs(dev, cdd);
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cppi_writel(0, cdd->qmgr_mem + QMGR_LRAM0_BASE);
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cppi_writel(0, cdd->qmgr_mem + QMGR_LRAM0_BASE);
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dma_free_coherent(&pdev->dev, QMGR_SCRATCH_SIZE, cdd->qmgr_scratch,
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dma_free_coherent(dev, QMGR_SCRATCH_SIZE, cdd->qmgr_scratch,
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cdd->scratch_phys);
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}
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static int init_descs(struct platform_device *pdev, struct cppi41_dd *cdd)
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static int init_descs(struct device *dev, struct cppi41_dd *cdd)
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{
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unsigned int desc_size;
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unsigned int mem_decs;
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@ -777,7 +777,7 @@ static int init_descs(struct platform_device *pdev, struct cppi41_dd *cdd)
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reg |= ilog2(ALLOC_DECS_NUM) - 5;
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BUILD_BUG_ON(DESCS_AREAS != 1);
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cdd->cd = dma_alloc_coherent(&pdev->dev, mem_decs,
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cdd->cd = dma_alloc_coherent(dev, mem_decs,
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&cdd->descs_phys, GFP_KERNEL);
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if (!cdd->cd)
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return -ENOMEM;
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@ -813,12 +813,12 @@ static void init_sched(struct cppi41_dd *cdd)
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cppi_writel(reg, cdd->sched_mem + DMA_SCHED_CTRL);
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}
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static int init_cppi41(struct platform_device *pdev, struct cppi41_dd *cdd)
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static int init_cppi41(struct device *dev, struct cppi41_dd *cdd)
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{
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int ret;
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BUILD_BUG_ON(QMGR_SCRATCH_SIZE > ((1 << 14) - 1));
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cdd->qmgr_scratch = dma_alloc_coherent(&pdev->dev, QMGR_SCRATCH_SIZE,
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cdd->qmgr_scratch = dma_alloc_coherent(dev, QMGR_SCRATCH_SIZE,
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&cdd->scratch_phys, GFP_KERNEL);
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if (!cdd->qmgr_scratch)
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return -ENOMEM;
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@ -827,7 +827,7 @@ static int init_cppi41(struct platform_device *pdev, struct cppi41_dd *cdd)
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cppi_writel(QMGR_SCRATCH_SIZE, cdd->qmgr_mem + QMGR_LRAM_SIZE);
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cppi_writel(0, cdd->qmgr_mem + QMGR_LRAM1_BASE);
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ret = init_descs(pdev, cdd);
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ret = init_descs(dev, cdd);
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if (ret)
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goto err_td;
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@ -835,7 +835,7 @@ static int init_cppi41(struct platform_device *pdev, struct cppi41_dd *cdd)
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init_sched(cdd);
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return 0;
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err_td:
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deinit_cpii41(pdev, cdd);
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deinit_cppi41(dev, cdd);
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return ret;
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}
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@ -914,11 +914,11 @@ static const struct of_device_id cppi41_dma_ids[] = {
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};
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MODULE_DEVICE_TABLE(of, cppi41_dma_ids);
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static const struct cppi_glue_infos *get_glue_info(struct platform_device *pdev)
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static const struct cppi_glue_infos *get_glue_info(struct device *dev)
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{
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const struct of_device_id *of_id;
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of_id = of_match_node(cppi41_dma_ids, pdev->dev.of_node);
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of_id = of_match_node(cppi41_dma_ids, dev->of_node);
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if (!of_id)
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return NULL;
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return of_id->data;
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@ -927,11 +927,12 @@ static const struct cppi_glue_infos *get_glue_info(struct platform_device *pdev)
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static int cppi41_dma_probe(struct platform_device *pdev)
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{
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struct cppi41_dd *cdd;
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struct device *dev = &pdev->dev;
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const struct cppi_glue_infos *glue_info;
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int irq;
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int ret;
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glue_info = get_glue_info(pdev);
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glue_info = get_glue_info(dev);
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if (!glue_info)
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return -EINVAL;
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@ -946,14 +947,14 @@ static int cppi41_dma_probe(struct platform_device *pdev)
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cdd->ddev.device_issue_pending = cppi41_dma_issue_pending;
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cdd->ddev.device_prep_slave_sg = cppi41_dma_prep_slave_sg;
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cdd->ddev.device_control = cppi41_dma_control;
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cdd->ddev.dev = &pdev->dev;
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cdd->ddev.dev = dev;
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INIT_LIST_HEAD(&cdd->ddev.channels);
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cpp41_dma_info.dma_cap = cdd->ddev.cap_mask;
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cdd->usbss_mem = of_iomap(pdev->dev.of_node, 0);
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cdd->ctrl_mem = of_iomap(pdev->dev.of_node, 1);
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cdd->sched_mem = of_iomap(pdev->dev.of_node, 2);
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cdd->qmgr_mem = of_iomap(pdev->dev.of_node, 3);
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cdd->usbss_mem = of_iomap(dev->of_node, 0);
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cdd->ctrl_mem = of_iomap(dev->of_node, 1);
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cdd->sched_mem = of_iomap(dev->of_node, 2);
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cdd->qmgr_mem = of_iomap(dev->of_node, 3);
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if (!cdd->usbss_mem || !cdd->ctrl_mem || !cdd->sched_mem ||
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!cdd->qmgr_mem) {
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@ -961,8 +962,8 @@ static int cppi41_dma_probe(struct platform_device *pdev)
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goto err_remap;
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}
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pm_runtime_enable(&pdev->dev);
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ret = pm_runtime_get_sync(&pdev->dev);
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pm_runtime_enable(dev);
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ret = pm_runtime_get_sync(dev);
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if (ret)
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goto err_get_sync;
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@ -970,22 +971,22 @@ static int cppi41_dma_probe(struct platform_device *pdev)
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cdd->queues_tx = glue_info->queues_tx;
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cdd->td_queue = glue_info->td_queue;
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ret = init_cppi41(pdev, cdd);
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ret = init_cppi41(dev, cdd);
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if (ret)
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goto err_init_cppi;
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ret = cppi41_add_chans(pdev, cdd);
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ret = cppi41_add_chans(dev, cdd);
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if (ret)
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goto err_chans;
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irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
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irq = irq_of_parse_and_map(dev->of_node, 0);
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if (!irq)
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goto err_irq;
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cppi_writel(USBSS_IRQ_PD_COMP, cdd->usbss_mem + USBSS_IRQ_ENABLER);
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ret = request_irq(irq, glue_info->isr, IRQF_SHARED,
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dev_name(&pdev->dev), cdd);
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dev_name(dev), cdd);
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if (ret)
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goto err_irq;
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cdd->irq = irq;
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@ -994,7 +995,7 @@ static int cppi41_dma_probe(struct platform_device *pdev)
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if (ret)
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goto err_dma_reg;
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ret = of_dma_controller_register(pdev->dev.of_node,
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ret = of_dma_controller_register(dev->of_node,
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cppi41_dma_xlate, &cpp41_dma_info);
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if (ret)
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goto err_of;
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@ -1009,11 +1010,11 @@ err_irq:
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cppi_writel(0, cdd->usbss_mem + USBSS_IRQ_CLEARR);
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cleanup_chans(cdd);
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err_chans:
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deinit_cpii41(pdev, cdd);
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deinit_cppi41(dev, cdd);
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err_init_cppi:
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pm_runtime_put(&pdev->dev);
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pm_runtime_put(dev);
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err_get_sync:
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pm_runtime_disable(&pdev->dev);
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pm_runtime_disable(dev);
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iounmap(cdd->usbss_mem);
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iounmap(cdd->ctrl_mem);
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iounmap(cdd->sched_mem);
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@ -1033,7 +1034,7 @@ static int cppi41_dma_remove(struct platform_device *pdev)
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cppi_writel(0, cdd->usbss_mem + USBSS_IRQ_CLEARR);
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free_irq(cdd->irq, cdd);
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cleanup_chans(cdd);
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deinit_cpii41(pdev, cdd);
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deinit_cppi41(&pdev->dev, cdd);
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iounmap(cdd->usbss_mem);
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iounmap(cdd->ctrl_mem);
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iounmap(cdd->sched_mem);
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@ -1044,12 +1045,41 @@ static int cppi41_dma_remove(struct platform_device *pdev)
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return 0;
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}
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#ifdef CONFIG_PM_SLEEP
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static int cppi41_suspend(struct device *dev)
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{
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struct cppi41_dd *cdd = dev_get_drvdata(dev);
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cppi_writel(0, cdd->usbss_mem + USBSS_IRQ_CLEARR);
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disable_sched(cdd);
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return 0;
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}
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static int cppi41_resume(struct device *dev)
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{
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struct cppi41_dd *cdd = dev_get_drvdata(dev);
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int i;
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|
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for (i = 0; i < DESCS_AREAS; i++)
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cppi_writel(cdd->descs_phys, cdd->qmgr_mem + QMGR_MEMBASE(i));
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init_sched(cdd);
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cppi_writel(USBSS_IRQ_PD_COMP, cdd->usbss_mem + USBSS_IRQ_ENABLER);
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|
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return 0;
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}
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#endif
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|
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static SIMPLE_DEV_PM_OPS(cppi41_pm_ops, cppi41_suspend, cppi41_resume);
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|
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static struct platform_driver cpp41_dma_driver = {
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.probe = cppi41_dma_probe,
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.remove = cppi41_dma_remove,
|
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.driver = {
|
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.name = "cppi41-dma-engine",
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.owner = THIS_MODULE,
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.pm = &cppi41_pm_ops,
|
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.of_match_table = of_match_ptr(cppi41_dma_ids),
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},
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};
|
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|
|
|
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|
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@ -46,8 +46,14 @@
|
|||
#define EDMA_CHANS 64
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#endif /* CONFIG_ARCH_DAVINCI_DA8XX */
|
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|
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/* Max of 16 segments per channel to conserve PaRAM slots */
|
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#define MAX_NR_SG 16
|
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/*
|
||||
* Max of 20 segments per channel to conserve PaRAM slots
|
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* Also note that MAX_NR_SG should be atleast the no.of periods
|
||||
* that are required for ASoC, otherwise DMA prep calls will
|
||||
* fail. Today davinci-pcm is the only user of this driver and
|
||||
* requires atleast 17 slots, so we setup the default to 20.
|
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*/
|
||||
#define MAX_NR_SG 20
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#define EDMA_MAX_SLOTS MAX_NR_SG
|
||||
#define EDMA_DESCRIPTORS 16
|
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|
||||
|
|
@ -250,6 +256,117 @@ static int edma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
|
|||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* A PaRAM set configuration abstraction used by other modes
|
||||
* @chan: Channel who's PaRAM set we're configuring
|
||||
* @pset: PaRAM set to initialize and setup.
|
||||
* @src_addr: Source address of the DMA
|
||||
* @dst_addr: Destination address of the DMA
|
||||
* @burst: In units of dev_width, how much to send
|
||||
* @dev_width: How much is the dev_width
|
||||
* @dma_length: Total length of the DMA transfer
|
||||
* @direction: Direction of the transfer
|
||||
*/
|
||||
static int edma_config_pset(struct dma_chan *chan, struct edmacc_param *pset,
|
||||
dma_addr_t src_addr, dma_addr_t dst_addr, u32 burst,
|
||||
enum dma_slave_buswidth dev_width, unsigned int dma_length,
|
||||
enum dma_transfer_direction direction)
|
||||
{
|
||||
struct edma_chan *echan = to_edma_chan(chan);
|
||||
struct device *dev = chan->device->dev;
|
||||
int acnt, bcnt, ccnt, cidx;
|
||||
int src_bidx, dst_bidx, src_cidx, dst_cidx;
|
||||
int absync;
|
||||
|
||||
acnt = dev_width;
|
||||
/*
|
||||
* If the maxburst is equal to the fifo width, use
|
||||
* A-synced transfers. This allows for large contiguous
|
||||
* buffer transfers using only one PaRAM set.
|
||||
*/
|
||||
if (burst == 1) {
|
||||
/*
|
||||
* For the A-sync case, bcnt and ccnt are the remainder
|
||||
* and quotient respectively of the division of:
|
||||
* (dma_length / acnt) by (SZ_64K -1). This is so
|
||||
* that in case bcnt over flows, we have ccnt to use.
|
||||
* Note: In A-sync tranfer only, bcntrld is used, but it
|
||||
* only applies for sg_dma_len(sg) >= SZ_64K.
|
||||
* In this case, the best way adopted is- bccnt for the
|
||||
* first frame will be the remainder below. Then for
|
||||
* every successive frame, bcnt will be SZ_64K-1. This
|
||||
* is assured as bcntrld = 0xffff in end of function.
|
||||
*/
|
||||
absync = false;
|
||||
ccnt = dma_length / acnt / (SZ_64K - 1);
|
||||
bcnt = dma_length / acnt - ccnt * (SZ_64K - 1);
|
||||
/*
|
||||
* If bcnt is non-zero, we have a remainder and hence an
|
||||
* extra frame to transfer, so increment ccnt.
|
||||
*/
|
||||
if (bcnt)
|
||||
ccnt++;
|
||||
else
|
||||
bcnt = SZ_64K - 1;
|
||||
cidx = acnt;
|
||||
} else {
|
||||
/*
|
||||
* If maxburst is greater than the fifo address_width,
|
||||
* use AB-synced transfers where A count is the fifo
|
||||
* address_width and B count is the maxburst. In this
|
||||
* case, we are limited to transfers of C count frames
|
||||
* of (address_width * maxburst) where C count is limited
|
||||
* to SZ_64K-1. This places an upper bound on the length
|
||||
* of an SG segment that can be handled.
|
||||
*/
|
||||
absync = true;
|
||||
bcnt = burst;
|
||||
ccnt = dma_length / (acnt * bcnt);
|
||||
if (ccnt > (SZ_64K - 1)) {
|
||||
dev_err(dev, "Exceeded max SG segment size\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
cidx = acnt * bcnt;
|
||||
}
|
||||
|
||||
if (direction == DMA_MEM_TO_DEV) {
|
||||
src_bidx = acnt;
|
||||
src_cidx = cidx;
|
||||
dst_bidx = 0;
|
||||
dst_cidx = 0;
|
||||
} else if (direction == DMA_DEV_TO_MEM) {
|
||||
src_bidx = 0;
|
||||
src_cidx = 0;
|
||||
dst_bidx = acnt;
|
||||
dst_cidx = cidx;
|
||||
} else {
|
||||
dev_err(dev, "%s: direction not implemented yet\n", __func__);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
pset->opt = EDMA_TCC(EDMA_CHAN_SLOT(echan->ch_num));
|
||||
/* Configure A or AB synchronized transfers */
|
||||
if (absync)
|
||||
pset->opt |= SYNCDIM;
|
||||
|
||||
pset->src = src_addr;
|
||||
pset->dst = dst_addr;
|
||||
|
||||
pset->src_dst_bidx = (dst_bidx << 16) | src_bidx;
|
||||
pset->src_dst_cidx = (dst_cidx << 16) | src_cidx;
|
||||
|
||||
pset->a_b_cnt = bcnt << 16 | acnt;
|
||||
pset->ccnt = ccnt;
|
||||
/*
|
||||
* Only time when (bcntrld) auto reload is required is for
|
||||
* A-sync case, and in this case, a requirement of reload value
|
||||
* of SZ_64K-1 only is assured. 'link' is initially set to NULL
|
||||
* and then later will be populated by edma_execute.
|
||||
*/
|
||||
pset->link_bcntrld = 0xffffffff;
|
||||
return absync;
|
||||
}
|
||||
|
||||
static struct dma_async_tx_descriptor *edma_prep_slave_sg(
|
||||
struct dma_chan *chan, struct scatterlist *sgl,
|
||||
unsigned int sg_len, enum dma_transfer_direction direction,
|
||||
|
|
@ -258,23 +375,21 @@ static struct dma_async_tx_descriptor *edma_prep_slave_sg(
|
|||
struct edma_chan *echan = to_edma_chan(chan);
|
||||
struct device *dev = chan->device->dev;
|
||||
struct edma_desc *edesc;
|
||||
dma_addr_t dev_addr;
|
||||
dma_addr_t src_addr = 0, dst_addr = 0;
|
||||
enum dma_slave_buswidth dev_width;
|
||||
u32 burst;
|
||||
struct scatterlist *sg;
|
||||
int acnt, bcnt, ccnt, src, dst, cidx;
|
||||
int src_bidx, dst_bidx, src_cidx, dst_cidx;
|
||||
int i, nslots;
|
||||
int i, nslots, ret;
|
||||
|
||||
if (unlikely(!echan || !sgl || !sg_len))
|
||||
return NULL;
|
||||
|
||||
if (direction == DMA_DEV_TO_MEM) {
|
||||
dev_addr = echan->cfg.src_addr;
|
||||
src_addr = echan->cfg.src_addr;
|
||||
dev_width = echan->cfg.src_addr_width;
|
||||
burst = echan->cfg.src_maxburst;
|
||||
} else if (direction == DMA_MEM_TO_DEV) {
|
||||
dev_addr = echan->cfg.dst_addr;
|
||||
dst_addr = echan->cfg.dst_addr;
|
||||
dev_width = echan->cfg.dst_addr_width;
|
||||
burst = echan->cfg.dst_maxburst;
|
||||
} else {
|
||||
|
|
@ -315,64 +430,21 @@ static struct dma_async_tx_descriptor *edma_prep_slave_sg(
|
|||
|
||||
/* Configure PaRAM sets for each SG */
|
||||
for_each_sg(sgl, sg, sg_len, i) {
|
||||
/* Get address for each SG */
|
||||
if (direction == DMA_DEV_TO_MEM)
|
||||
dst_addr = sg_dma_address(sg);
|
||||
else
|
||||
src_addr = sg_dma_address(sg);
|
||||
|
||||
acnt = dev_width;
|
||||
|
||||
/*
|
||||
* If the maxburst is equal to the fifo width, use
|
||||
* A-synced transfers. This allows for large contiguous
|
||||
* buffer transfers using only one PaRAM set.
|
||||
*/
|
||||
if (burst == 1) {
|
||||
edesc->absync = false;
|
||||
ccnt = sg_dma_len(sg) / acnt / (SZ_64K - 1);
|
||||
bcnt = sg_dma_len(sg) / acnt - ccnt * (SZ_64K - 1);
|
||||
if (bcnt)
|
||||
ccnt++;
|
||||
else
|
||||
bcnt = SZ_64K - 1;
|
||||
cidx = acnt;
|
||||
/*
|
||||
* If maxburst is greater than the fifo address_width,
|
||||
* use AB-synced transfers where A count is the fifo
|
||||
* address_width and B count is the maxburst. In this
|
||||
* case, we are limited to transfers of C count frames
|
||||
* of (address_width * maxburst) where C count is limited
|
||||
* to SZ_64K-1. This places an upper bound on the length
|
||||
* of an SG segment that can be handled.
|
||||
*/
|
||||
} else {
|
||||
edesc->absync = true;
|
||||
bcnt = burst;
|
||||
ccnt = sg_dma_len(sg) / (acnt * bcnt);
|
||||
if (ccnt > (SZ_64K - 1)) {
|
||||
dev_err(dev, "Exceeded max SG segment size\n");
|
||||
kfree(edesc);
|
||||
return NULL;
|
||||
}
|
||||
cidx = acnt * bcnt;
|
||||
ret = edma_config_pset(chan, &edesc->pset[i], src_addr,
|
||||
dst_addr, burst, dev_width,
|
||||
sg_dma_len(sg), direction);
|
||||
if (ret < 0) {
|
||||
kfree(edesc);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
if (direction == DMA_MEM_TO_DEV) {
|
||||
src = sg_dma_address(sg);
|
||||
dst = dev_addr;
|
||||
src_bidx = acnt;
|
||||
src_cidx = cidx;
|
||||
dst_bidx = 0;
|
||||
dst_cidx = 0;
|
||||
} else {
|
||||
src = dev_addr;
|
||||
dst = sg_dma_address(sg);
|
||||
src_bidx = 0;
|
||||
src_cidx = 0;
|
||||
dst_bidx = acnt;
|
||||
dst_cidx = cidx;
|
||||
}
|
||||
|
||||
edesc->pset[i].opt = EDMA_TCC(EDMA_CHAN_SLOT(echan->ch_num));
|
||||
/* Configure A or AB synchronized transfers */
|
||||
if (edesc->absync)
|
||||
edesc->pset[i].opt |= SYNCDIM;
|
||||
edesc->absync = ret;
|
||||
|
||||
/* If this is the last in a current SG set of transactions,
|
||||
enable interrupts so that next set is processed */
|
||||
|
|
@ -382,17 +454,6 @@ static struct dma_async_tx_descriptor *edma_prep_slave_sg(
|
|||
/* If this is the last set, enable completion interrupt flag */
|
||||
if (i == sg_len - 1)
|
||||
edesc->pset[i].opt |= TCINTEN;
|
||||
|
||||
edesc->pset[i].src = src;
|
||||
edesc->pset[i].dst = dst;
|
||||
|
||||
edesc->pset[i].src_dst_bidx = (dst_bidx << 16) | src_bidx;
|
||||
edesc->pset[i].src_dst_cidx = (dst_cidx << 16) | src_cidx;
|
||||
|
||||
edesc->pset[i].a_b_cnt = bcnt << 16 | acnt;
|
||||
edesc->pset[i].ccnt = ccnt;
|
||||
edesc->pset[i].link_bcntrld = 0xffffffff;
|
||||
|
||||
}
|
||||
|
||||
return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
|
||||
|
|
|
|||
|
|
@ -693,7 +693,7 @@ static int k3_dma_probe(struct platform_device *op)
|
|||
|
||||
irq = platform_get_irq(op, 0);
|
||||
ret = devm_request_irq(&op->dev, irq,
|
||||
k3_dma_int_handler, IRQF_DISABLED, DRIVER_NAME, d);
|
||||
k3_dma_int_handler, 0, DRIVER_NAME, d);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
|
|
|
|||
|
|
@ -798,8 +798,7 @@ static void dma_do_tasklet(unsigned long data)
|
|||
* move the descriptors to a temporary list so we can drop
|
||||
* the lock during the entire cleanup operation
|
||||
*/
|
||||
list_del(&desc->node);
|
||||
list_add(&desc->node, &chain_cleanup);
|
||||
list_move(&desc->node, &chain_cleanup);
|
||||
|
||||
/*
|
||||
* Look for the first list entry which has the ENDIRQEN flag
|
||||
|
|
@ -863,7 +862,7 @@ static int mmp_pdma_chan_init(struct mmp_pdma_device *pdev,
|
|||
|
||||
if (irq) {
|
||||
ret = devm_request_irq(pdev->dev, irq,
|
||||
mmp_pdma_chan_handler, IRQF_DISABLED, "pdma", phy);
|
||||
mmp_pdma_chan_handler, 0, "pdma", phy);
|
||||
if (ret) {
|
||||
dev_err(pdev->dev, "channel request irq fail!\n");
|
||||
return ret;
|
||||
|
|
@ -970,7 +969,7 @@ static int mmp_pdma_probe(struct platform_device *op)
|
|||
/* all chan share one irq, demux inside */
|
||||
irq = platform_get_irq(op, 0);
|
||||
ret = devm_request_irq(pdev->dev, irq,
|
||||
mmp_pdma_int_handler, IRQF_DISABLED, "pdma", pdev);
|
||||
mmp_pdma_int_handler, 0, "pdma", pdev);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -62,6 +62,11 @@
|
|||
#define TDCR_BURSTSZ_16B (0x3 << 6)
|
||||
#define TDCR_BURSTSZ_32B (0x6 << 6)
|
||||
#define TDCR_BURSTSZ_64B (0x7 << 6)
|
||||
#define TDCR_BURSTSZ_SQU_1B (0x5 << 6)
|
||||
#define TDCR_BURSTSZ_SQU_2B (0x6 << 6)
|
||||
#define TDCR_BURSTSZ_SQU_4B (0x0 << 6)
|
||||
#define TDCR_BURSTSZ_SQU_8B (0x1 << 6)
|
||||
#define TDCR_BURSTSZ_SQU_16B (0x3 << 6)
|
||||
#define TDCR_BURSTSZ_SQU_32B (0x7 << 6)
|
||||
#define TDCR_BURSTSZ_128B (0x5 << 6)
|
||||
#define TDCR_DSTDIR_MSK (0x3 << 4) /* Dst Direction */
|
||||
|
|
@ -228,8 +233,31 @@ static int mmp_tdma_config_chan(struct mmp_tdma_chan *tdmac)
|
|||
return -EINVAL;
|
||||
}
|
||||
} else if (tdmac->type == PXA910_SQU) {
|
||||
tdcr |= TDCR_BURSTSZ_SQU_32B;
|
||||
tdcr |= TDCR_SSPMOD;
|
||||
|
||||
switch (tdmac->burst_sz) {
|
||||
case 1:
|
||||
tdcr |= TDCR_BURSTSZ_SQU_1B;
|
||||
break;
|
||||
case 2:
|
||||
tdcr |= TDCR_BURSTSZ_SQU_2B;
|
||||
break;
|
||||
case 4:
|
||||
tdcr |= TDCR_BURSTSZ_SQU_4B;
|
||||
break;
|
||||
case 8:
|
||||
tdcr |= TDCR_BURSTSZ_SQU_8B;
|
||||
break;
|
||||
case 16:
|
||||
tdcr |= TDCR_BURSTSZ_SQU_16B;
|
||||
break;
|
||||
case 32:
|
||||
tdcr |= TDCR_BURSTSZ_SQU_32B;
|
||||
break;
|
||||
default:
|
||||
dev_err(tdmac->dev, "mmp_tdma: unknown burst size.\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
writel(tdcr, tdmac->reg_base + TDCR);
|
||||
|
|
@ -324,7 +352,7 @@ static int mmp_tdma_alloc_chan_resources(struct dma_chan *chan)
|
|||
|
||||
if (tdmac->irq) {
|
||||
ret = devm_request_irq(tdmac->dev, tdmac->irq,
|
||||
mmp_tdma_chan_handler, IRQF_DISABLED, "tdma", tdmac);
|
||||
mmp_tdma_chan_handler, 0, "tdma", tdmac);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -559,7 +587,7 @@ static int mmp_tdma_probe(struct platform_device *pdev)
|
|||
if (irq_num != chan_num) {
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
ret = devm_request_irq(&pdev->dev, irq,
|
||||
mmp_tdma_int_handler, IRQF_DISABLED, "tdma", tdev);
|
||||
mmp_tdma_int_handler, 0, "tdma", tdev);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -2922,16 +2922,23 @@ pl330_probe(struct amba_device *adev, const struct amba_id *id)
|
|||
|
||||
amba_set_drvdata(adev, pdmac);
|
||||
|
||||
irq = adev->irq[0];
|
||||
ret = request_irq(irq, pl330_irq_handler, 0,
|
||||
dev_name(&adev->dev), pi);
|
||||
if (ret)
|
||||
return ret;
|
||||
for (i = 0; i <= AMBA_NR_IRQS; i++) {
|
||||
irq = adev->irq[i];
|
||||
if (irq) {
|
||||
ret = devm_request_irq(&adev->dev, irq,
|
||||
pl330_irq_handler, 0,
|
||||
dev_name(&adev->dev), pi);
|
||||
if (ret)
|
||||
return ret;
|
||||
} else {
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
pi->pcfg.periph_id = adev->periphid;
|
||||
ret = pl330_add(pi);
|
||||
if (ret)
|
||||
goto probe_err1;
|
||||
return ret;
|
||||
|
||||
INIT_LIST_HEAD(&pdmac->desc_pool);
|
||||
spin_lock_init(&pdmac->pool_lock);
|
||||
|
|
@ -3044,8 +3051,6 @@ probe_err3:
|
|||
}
|
||||
probe_err2:
|
||||
pl330_del(pi);
|
||||
probe_err1:
|
||||
free_irq(irq, pi);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -3055,7 +3060,6 @@ static int pl330_remove(struct amba_device *adev)
|
|||
struct dma_pl330_dmac *pdmac = amba_get_drvdata(adev);
|
||||
struct dma_pl330_chan *pch, *_p;
|
||||
struct pl330_info *pi;
|
||||
int irq;
|
||||
|
||||
if (!pdmac)
|
||||
return 0;
|
||||
|
|
@ -3082,9 +3086,6 @@ static int pl330_remove(struct amba_device *adev)
|
|||
|
||||
pl330_del(pi);
|
||||
|
||||
irq = adev->irq[0];
|
||||
free_irq(irq, pi);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -685,7 +685,7 @@ MODULE_DEVICE_TABLE(of, sh_dmae_of_match);
|
|||
static int sh_dmae_probe(struct platform_device *pdev)
|
||||
{
|
||||
const struct sh_dmae_pdata *pdata;
|
||||
unsigned long irqflags = IRQF_DISABLED,
|
||||
unsigned long irqflags = 0,
|
||||
chan_flag[SH_DMAE_MAX_CHANNELS] = {};
|
||||
int errirq, chan_irq[SH_DMAE_MAX_CHANNELS];
|
||||
int err, i, irq_cnt = 0, irqres = 0, irq_cap = 0;
|
||||
|
|
@ -838,7 +838,7 @@ static int sh_dmae_probe(struct platform_device *pdev)
|
|||
IORESOURCE_IRQ_SHAREABLE)
|
||||
chan_flag[irq_cnt] = IRQF_SHARED;
|
||||
else
|
||||
chan_flag[irq_cnt] = IRQF_DISABLED;
|
||||
chan_flag[irq_cnt] = 0;
|
||||
dev_dbg(&pdev->dev,
|
||||
"Found IRQ %d for channel %d\n",
|
||||
i, irq_cnt);
|
||||
|
|
|
|||
|
|
@ -14,6 +14,7 @@
|
|||
#include <linux/platform_device.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/log2.h>
|
||||
#include <linux/pm.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
#include <linux/err.h>
|
||||
|
|
@ -2796,8 +2797,8 @@ static int d40_set_runtime_config(struct dma_chan *chan,
|
|||
src_addr_width > DMA_SLAVE_BUSWIDTH_8_BYTES ||
|
||||
dst_addr_width <= DMA_SLAVE_BUSWIDTH_UNDEFINED ||
|
||||
dst_addr_width > DMA_SLAVE_BUSWIDTH_8_BYTES ||
|
||||
((src_addr_width > 1) && (src_addr_width & 1)) ||
|
||||
((dst_addr_width > 1) && (dst_addr_width & 1)))
|
||||
!is_power_of_2(src_addr_width) ||
|
||||
!is_power_of_2(dst_addr_width))
|
||||
return -EINVAL;
|
||||
|
||||
cfg->src_info.data_width = src_addr_width;
|
||||
|
|
|
|||
|
|
@ -1018,7 +1018,7 @@ static struct dma_async_tx_descriptor *tegra_dma_prep_slave_sg(
|
|||
return &dma_desc->txd;
|
||||
}
|
||||
|
||||
struct dma_async_tx_descriptor *tegra_dma_prep_dma_cyclic(
|
||||
static struct dma_async_tx_descriptor *tegra_dma_prep_dma_cyclic(
|
||||
struct dma_chan *dc, dma_addr_t buf_addr, size_t buf_len,
|
||||
size_t period_len, enum dma_transfer_direction direction,
|
||||
unsigned long flags, void *context)
|
||||
|
|
|
|||
Loading…
Reference in a new issue