OMAP3: ASM sleep code format rework
Cosmetic fixes to the code: - white spaces and tabs, - alignement, - comments rephrase and typos, - multi-line comments Tested on N900 and Beagleboard with full RET and OFF modes, using cpuidle and suspend. Signed-off-by: Jean Pihet <j-pihet@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Nishanth Menon <nm@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
This commit is contained in:
Jean Pihet
Kevin Hilman
parent
8352129166
commit
bb1c9034b3
1 changed files with 117 additions and 107 deletions
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@ -1,6 +1,4 @@
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/*
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* linux/arch/arm/mach-omap2/sleep.S
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*
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* (C) Copyright 2007
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* Texas Instruments
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* Karthik Dasu <karthik-dp@ti.com>
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@ -118,10 +116,10 @@ ENTRY(enable_omap3630_toggle_l2_on_restore)
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str r1, l2dis_3630
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ldmfd sp!, {pc} @ restore regs and return
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.text
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/* Function to call rom code to save secure ram context */
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ENTRY(save_secure_ram_context)
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stmfd sp!, {r1-r12, lr} @ save registers on stack
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adr r3, api_params @ r3 points to parameters
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str r0, [r3,#0x4] @ r0 has sdram address
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ldr r12, high_mask
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@ -165,8 +163,8 @@ ENTRY(save_secure_ram_context_sz)
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*
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*
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* Notes:
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* - this code gets copied to internal SRAM at boot. The execution pointer
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* in SRAM is _omap_sram_idle.
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* - this code gets copied to internal SRAM at boot and after wake-up
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* from OFF mode. The execution pointer in SRAM is _omap_sram_idle.
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* - when the OMAP wakes up it continues at different execution points
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* depending on the low power mode (non-OFF vs OFF modes),
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* cf. 'Resume path for xxx mode' comments.
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@ -439,12 +437,13 @@ skipl2dis:
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.word 0xE1600071 @ call SMI monitor (smi #1)
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#endif
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b logic_l1_restore
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l2_inv_api_params:
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.word 0x1, 0x00
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l2_inv_gp:
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/* Execute smi to invalidate L2 cache */
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mov r12, #0x1 @ set up to invalide L2
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smi: .word 0xE1600070 @ Call SMI monitor (smieq)
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mov r12, #0x1 @ set up to invalidate L2
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.word 0xE1600070 @ Call SMI monitor (smieq)
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/* Write to Aux control register to set some bits */
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ldr r4, scratchpad_base
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ldr r3, [r4,#0xBC]
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@ -458,15 +457,17 @@ smi: .word 0xE1600070 @ Call SMI monitor (smieq)
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.word 0xE1600070 @ Call SMI monitor (smieq)
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logic_l1_restore:
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ldr r1, l2dis_3630
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cmp r1, #0x1 @ Do we need to re-enable L2 on 3630?
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cmp r1, #0x1 @ Test if L2 re-enable needed on 3630
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bne skipl2reen
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mrc p15, 0, r1, c1, c0, 1
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orr r1, r1, #2 @ re-enable L2 cache
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mcr p15, 0, r1, c1, c0, 1
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skipl2reen:
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mov r1, #0
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/* Invalidate all instruction caches to PoU
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* and flush branch target cache */
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/*
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* Invalidate all instruction caches to PoU
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* and flush branch target cache
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*/
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mcr p15, 0, r1, c7, c5, 0
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ldr r4, scratchpad_base
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@ -487,31 +488,31 @@ skipl2reen:
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MCR p15, 0, r6, c2, c0, 1
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/* Translation table base control register */
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MCR p15, 0, r7, c2, c0, 2
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/*domain access Control Register */
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/* Domain access Control Register */
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MCR p15, 0, r8, c3, c0, 0
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/* data fault status Register */
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/* Data fault status Register */
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MCR p15, 0, r9, c5, c0, 0
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ldmia r3!,{r4-r8}
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/* instruction fault status Register */
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/* Instruction fault status Register */
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MCR p15, 0, r4, c5, c0, 1
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/*Data Auxiliary Fault Status Register */
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/* Data Auxiliary Fault Status Register */
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MCR p15, 0, r5, c5, c1, 0
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/*Instruction Auxiliary Fault Status Register*/
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/* Instruction Auxiliary Fault Status Register*/
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MCR p15, 0, r6, c5, c1, 1
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/*Data Fault Address Register */
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/* Data Fault Address Register */
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MCR p15, 0, r7, c6, c0, 0
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/*Instruction Fault Address Register*/
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/* Instruction Fault Address Register*/
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MCR p15, 0, r8, c6, c0, 2
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ldmia r3!,{r4-r7}
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/* user r/w thread and process ID */
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/* User r/w thread and process ID */
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MCR p15, 0, r4, c13, c0, 2
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/* user ro thread and process ID */
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/* User ro thread and process ID */
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MCR p15, 0, r5, c13, c0, 3
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/*Privileged only thread and process ID */
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/* Privileged only thread and process ID */
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MCR p15, 0, r6, c13, c0, 4
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/* cache size selection */
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/* Cache size selection */
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MCR p15, 2, r7, c0, c0, 0
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ldmia r3!,{r4-r8}
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/* Data TLB lockdown registers */
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@ -526,23 +527,24 @@ skipl2reen:
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MCR p15, 0, r8, c13, c0, 1
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ldmia r3!,{r4-r5}
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/* primary memory remap register */
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/* Primary memory remap register */
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MCR p15, 0, r4, c10, c2, 0
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/*normal memory remap register */
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/* Normal memory remap register */
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MCR p15, 0, r5, c10, c2, 1
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/* Restore cpsr */
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ldmia r3!,{r4} /*load CPSR from SDRAM*/
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msr cpsr, r4 /*store cpsr */
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ldmia r3!,{r4} @ load CPSR from SDRAM
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msr cpsr, r4 @ store cpsr
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/* Enabling MMU here */
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mrc p15, 0, r7, c2, c0, 2 /* Read TTBRControl */
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/* Extract N (0:2) bits and decide whether to use TTBR0 or TTBR1*/
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mrc p15, 0, r7, c2, c0, 2 @ Read TTBRControl
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/* Extract N (0:2) bits and decide whether to use TTBR0 or TTBR1 */
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and r7, #0x7
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cmp r7, #0x0
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beq usettbr0
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ttbr_error:
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/* More work needs to be done to support N[0:2] value other than 0
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/*
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* More work needs to be done to support N[0:2] value other than 0
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* So looping here so that the error can be detected
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*/
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b ttbr_error
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@ -552,21 +554,25 @@ usettbr0:
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and r2, r5
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mov r4, pc
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ldr r5, table_index_mask
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and r4, r5 /* r4 = 31 to 20 bits of pc */
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and r4, r5 @ r4 = 31 to 20 bits of pc
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/* Extract the value to be written to table entry */
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ldr r1, table_entry
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add r1, r1, r4 /* r1 has value to be written to table entry*/
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/* r1 has the value to be written to table entry*/
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add r1, r1, r4
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/* Getting the address of table entry to modify */
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lsr r4, #18
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add r2, r4 /* r2 has the location which needs to be modified */
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/* r2 has the location which needs to be modified */
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add r2, r4
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/* Storing previous entry of location being modified */
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ldr r5, scratchpad_base
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ldr r4, [r2]
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str r4, [r5, #0xC0]
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/* Modify the table entry */
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str r1, [r2]
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/* Storing address of entry being modified
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* - will be restored after enabling MMU */
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/*
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* Storing address of entry being modified
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* - will be restored after enabling MMU
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*/
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ldr r5, scratchpad_base
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str r2, [r5, #0xC4]
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@ -575,8 +581,11 @@ usettbr0:
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mcr p15, 0, r0, c7, c5, 6 @ Invalidate branch predictor array
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mcr p15, 0, r0, c8, c5, 0 @ Invalidate instruction TLB
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mcr p15, 0, r0, c8, c6, 0 @ Invalidate data TLB
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/* Restore control register but dont enable caches here*/
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/* Caches will be enabled after restoring MMU table entry */
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/*
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* Restore control register. This enables the MMU.
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* The caches and prediction are not enabled here, they
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* will be enabled after restoring the MMU table entry.
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*/
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ldmia r3!, {r4}
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/* Store previous value of control register in scratchpad */
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str r4, [r5, #0xC8]
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@ -655,7 +664,7 @@ ENTRY(es3_sdrc_fix_sz)
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/* Make sure SDRC accesses are ok */
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wait_sdrc_ok:
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/* DPLL3 must be locked before accessing the SDRC. Maybe the HW ensures this. */
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/* DPLL3 must be locked before accessing the SDRC. Maybe the HW ensures this */
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ldr r4, cm_idlest_ckgen
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wait_dpll3_lock:
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ldr r5, [r4]
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@ -672,20 +681,21 @@ wait_sdrc_ready:
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ldr r5, [r4]
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bic r5, r5, #0x40
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str r5, [r4]
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is_dll_in_lock_mode:
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is_dll_in_lock_mode:
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/* Is dll in lock mode? */
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ldr r4, sdrc_dlla_ctrl
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ldr r5, [r4]
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tst r5, #0x4
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bxne lr
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bxne lr @ Return if locked
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/* wait till dll locks */
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wait_dll_lock_timed:
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ldr r4, wait_dll_lock_counter
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add r4, r4, #1
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str r4, wait_dll_lock_counter
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ldr r4, sdrc_dlla_status
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mov r6, #8 /* Wait 20uS for lock */
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/* Wait 20uS for lock */
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mov r6, #8
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wait_dll_lock:
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subs r6, r6, #0x1
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beq kick_dll
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@ -693,17 +703,17 @@ wait_dll_lock:
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and r5, r5, #0x4
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cmp r5, #0x4
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bne wait_dll_lock
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bx lr
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bx lr @ Return when locked
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/* disable/reenable DLL if not locked */
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kick_dll:
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ldr r4, sdrc_dlla_ctrl
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ldr r5, [r4]
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mov r6, r5
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bic r6, #(1<<3) /* disable dll */
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bic r6, #(1<<3) @ disable dll
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str r6, [r4]
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dsb
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orr r6, r6, #(1<<3) /* enable dll */
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orr r6, r6, #(1<<3) @ enable dll
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str r6, [r4]
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dsb
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ldr r4, kick_counter
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