kpriv/linux-hardened
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

drm/i915: don't enable PM_VEBOX_CS_ERROR_INTERRUPT

Browse source 
The code to handle it is broken - there's simply no code to clear CS
parser errors on gen5+. And behold, for all the other rings we also
don't enable it!

Leave the handling code itself in place just to be consistent with the
existing mess though. And in case someone feels like fixing it all up.

This has been errornously enabled in

commit 12638c57f3
Author: Ben Widawsky <ben@bwidawsk.net>
Date:   Tue May 28 19:22:31 2013 -0700

    drm/i915: Enable vebox interrupts

Cc: Damien Lespiau <damien.lespiau@intel.com>
Cc: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Daniel Vetter 2013-07-04 23:35:30 +02:00
parent c7113cc35f
commit c0d6a3dd61
2 changed files with 2 additions and 4 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

3
drivers/gpu/drm/i915/i915_irq.c
View file

@ -2814,8 +2814,7 @@ static int ivybridge_irq_postinstall(struct drm_device *dev)
I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
if (HAS_VEBOX(dev))
pm_irqs |= PM_VEBOX_USER_INTERRUPT |
PM_VEBOX_CS_ERROR_INTERRUPT;
pm_irqs |= PM_VEBOX_USER_INTERRUPT;
/* Our enable/disable rps functions may touch these registers so
* make sure to set a known state for only the non-RPS bits.

3
drivers/gpu/drm/i915/intel_ringbuffer.c
View file

@ -2000,8 +2000,7 @@ int intel_init_vebox_ring_buffer(struct drm_device *dev)
ring->add_request = gen6_add_request;
ring->get_seqno = gen6_ring_get_seqno;
ring->set_seqno = ring_set_seqno;
ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT |
PM_VEBOX_CS_ERROR_INTERRUPT;
ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
ring->irq_get = hsw_vebox_get_irq;
ring->irq_put = hsw_vebox_put_irq;
ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;