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Omap fixes for issues noted during the merge window, mostly

Browse source 
PM related.
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Merge tag 'omap-fixes-for-v3.6-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into fixes

Omap fixes for issues noted during the merge window, mostly
PM related.

* tag 'omap-fixes-for-v3.6-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  ARM: OMAP: dmtimers: Fix locking issue in omap_dm_timer_request*()
  ARM: OMAP4: Register the OPP table only for 4430 device
  cpufreq: OMAP: Handle missing frequency table on SMP systems
  ARM: OMAP4: sleep: Save the complete used register stack frame
  ARM: OMAP2+: cpu: Add am33xx device under cpu_class_is_omap2
  omap: Fix multi.h when only ARCH_OMAP3 and SOC_AM33XX are selected
  ARM: OMAP2+: Fix dmtimer set source clock failure
  Revert "ARM: OMAP3: PM: call pre/post transition per powerdomain"
  ARM: OMAP3: TWL4030: ensure sys_nirq1 is mux'd and wakeup enabled
  omap2: mux: remove comment for nonexistent member
  OMAP: remove unused parameter arch_id from uncompress.h
  arm/dts: Mark vcxio, v2v1 and v1v8 regulators as always on
  OMAP2+: Fix random config build break with !ARM_CPU_SUSPEND
  arm/dts: Fix am33xx wdt node
  ARM: OMAP3: igep0020: set GPIO mode for mux mcspi1_cs2 pin
  Revert "ARM: OMAP3530evm: set pendown_state and debounce time for ads7846"

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2012-08-15 14:31:25 +02:00
commit c6041d4add
17 changed files with 43 additions and 40 deletions
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5
arch/arm/boot/dts/am33xx.dtsi
View file

@ -154,5 +154,10 @@
#size-cells = <0>;
ti,hwmods = "i2c3";
};
wdt2: wdt@44e35000 {
compatible = "ti,omap3-wdt";
ti,hwmods = "wd_timer2";
};
};
};

3
arch/arm/boot/dts/twl6030.dtsi
View file

@ -66,6 +66,7 @@
vcxio: regulator@8 {
compatible = "ti,twl6030-vcxio";
regulator-always-on;
};
vusb: regulator@9 {
@ -74,10 +75,12 @@
v1v8: regulator@10 {
compatible = "ti,twl6030-v1v8";
regulator-always-on;
};
v2v1: regulator@11 {
compatible = "ti,twl6030-v2v1";
regulator-always-on;
};
clk32kg: regulator@12 {

1
arch/arm/mach-omap2/Kconfig
View file

@ -69,6 +69,7 @@ config SOC_OMAP5
select CPU_V7
select ARM_GIC
select HAVE_SMP
select ARM_CPU_SUSPEND if PM
comment "OMAP Core Type"
depends on ARCH_OMAP2

2
arch/arm/mach-omap2/board-igep0020.c
View file

@ -554,6 +554,8 @@ static const struct usbhs_omap_board_data igep3_usbhs_bdata __initconst = {
#ifdef CONFIG_OMAP_MUX
static struct omap_board_mux board_mux[] __initdata = {
/* SMSC9221 LAN Controller ETH IRQ (GPIO_176) */
OMAP3_MUX(MCSPI1_CS2, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
#endif

1
arch/arm/mach-omap2/board-omap3evm.c
View file

@ -58,6 +58,7 @@
#include "hsmmc.h"
#include "common-board-devices.h"
#define OMAP3_EVM_TS_GPIO 175
#define OMAP3_EVM_EHCI_VBUS 22
#define OMAP3_EVM_EHCI_SELECT 61

11
arch/arm/mach-omap2/common-board-devices.c
View file

@ -35,16 +35,6 @@ static struct omap2_mcspi_device_config ads7846_mcspi_config = {
.turbo_mode = 0,
};
/*
* ADS7846 driver maybe request a gpio according to the value
* of pdata->get_pendown_state, but we have done this. So set
* get_pendown_state to avoid twice gpio requesting.
*/
static int omap3_get_pendown_state(void)
{
return !gpio_get_value(OMAP3_EVM_TS_GPIO);
}
static struct ads7846_platform_data ads7846_config = {
.x_max = 0x0fff,
.y_max = 0x0fff,
@ -55,7 +45,6 @@ static struct ads7846_platform_data ads7846_config = {
.debounce_rep = 1,
.gpio_pendown = -EINVAL,
.keep_vref_on = 1,
.get_pendown_state = &omap3_get_pendown_state,
};
static struct spi_board_info ads7846_spi_board_info __initdata = {

1
arch/arm/mach-omap2/common-board-devices.h
View file

@ -4,7 +4,6 @@
#include "twl-common.h"
#define NAND_BLOCK_SIZE SZ_128K
#define OMAP3_EVM_TS_GPIO 175
struct mtd_partition;
struct ads7846_platform_data;

1
arch/arm/mach-omap2/mux.h
View file

@ -127,7 +127,6 @@ struct omap_mux_partition {
* @gpio: GPIO number
* @muxnames: available signal modes for a ball
* @balls: available balls on the package
* @partition: mux partition
*/
struct omap_mux {
u16 reg_offset;

2
arch/arm/mach-omap2/opp4xxx_data.c
View file

@ -94,7 +94,7 @@ int __init omap4_opp_init(void)
{
int r = -ENODEV;
if (!cpu_is_omap44xx())
if (!cpu_is_omap443x())
return r;
r = omap_init_opp_table(omap44xx_opp_def_list,

21
arch/arm/mach-omap2/pm34xx.c
View file

@ -272,21 +272,16 @@ void omap_sram_idle(void)
per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
if (mpu_next_state < PWRDM_POWER_ON) {
pwrdm_pre_transition(mpu_pwrdm);
pwrdm_pre_transition(neon_pwrdm);
}
pwrdm_pre_transition(NULL);
/* PER */
if (per_next_state < PWRDM_POWER_ON) {
pwrdm_pre_transition(per_pwrdm);
per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0;
omap2_gpio_prepare_for_idle(per_going_off);
}
/* CORE */
if (core_next_state < PWRDM_POWER_ON) {
pwrdm_pre_transition(core_pwrdm);
if (core_next_state == PWRDM_POWER_OFF) {
omap3_core_save_context();
omap3_cm_save_context();
@ -339,20 +334,14 @@ void omap_sram_idle(void)
omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
OMAP3430_GR_MOD,
OMAP3_PRM_VOLTCTRL_OFFSET);
pwrdm_post_transition(core_pwrdm);
}
omap3_intc_resume_idle();
/* PER */
if (per_next_state < PWRDM_POWER_ON) {
omap2_gpio_resume_after_idle();
pwrdm_post_transition(per_pwrdm);
}
pwrdm_post_transition(NULL);
if (mpu_next_state < PWRDM_POWER_ON) {
pwrdm_post_transition(mpu_pwrdm);
pwrdm_post_transition(neon_pwrdm);
}
/* PER */
if (per_next_state < PWRDM_POWER_ON)
omap2_gpio_resume_after_idle();
}
static void omap3_pm_idle(void)

8
arch/arm/mach-omap2/sleep44xx.S
View file

@ -56,9 +56,13 @@ ppa_por_params:
* The restore function pointer is stored at CPUx_WAKEUP_NS_PA_ADDR_OFFSET.
* It returns to the caller for CPU INACTIVE and ON power states or in case
* CPU failed to transition to targeted OFF/DORMANT state.
*
* omap4_finish_suspend() calls v7_flush_dcache_all() which doesn't save
* stack frame and it expects the caller to take care of it. Hence the entire
* stack frame is saved to avoid possible stack corruption.
*/
ENTRY(omap4_finish_suspend)
stmfd sp!, {lr}
stmfd sp!, {r4-r12, lr}
cmp r0, #0x0
beq do_WFI @ No lowpower state, jump to WFI
@ -226,7 +230,7 @@ scu_gp_clear:
skip_scu_gp_clear:
isb
dsb
ldmfd sp!, {pc}
ldmfd sp!, {r4-r12, pc}
ENDPROC(omap4_finish_suspend)
/*

1
arch/arm/mach-omap2/twl-common.c
View file

@ -67,6 +67,7 @@ void __init omap_pmic_init(int bus, u32 clkrate,
const char *pmic_type, int pmic_irq,
struct twl4030_platform_data *pmic_data)
{
omap_mux_init_signal("sys_nirq", OMAP_PIN_INPUT_PULLUP | OMAP_PIN_OFF_WAKEUPENABLE);
strncpy(pmic_i2c_board_info.type, pmic_type,
sizeof(pmic_i2c_board_info.type));
pmic_i2c_board_info.irq = pmic_irq;

6
arch/arm/plat-omap/dmtimer.c
View file

@ -189,6 +189,7 @@ struct omap_dm_timer *omap_dm_timer_request(void)
timer->reserved = 1;
break;
}
spin_unlock_irqrestore(&dm_timer_lock, flags);
if (timer) {
ret = omap_dm_timer_prepare(timer);
@ -197,7 +198,6 @@ struct omap_dm_timer *omap_dm_timer_request(void)
timer = NULL;
}
}
spin_unlock_irqrestore(&dm_timer_lock, flags);
if (!timer)
pr_debug("%s: timer request failed!\n", __func__);
@ -220,6 +220,7 @@ struct omap_dm_timer *omap_dm_timer_request_specific(int id)
break;
}
}
spin_unlock_irqrestore(&dm_timer_lock, flags);
if (timer) {
ret = omap_dm_timer_prepare(timer);
@ -228,7 +229,6 @@ struct omap_dm_timer *omap_dm_timer_request_specific(int id)
timer = NULL;
}
}
spin_unlock_irqrestore(&dm_timer_lock, flags);
if (!timer)
pr_debug("%s: timer%d request failed!\n", __func__, id);
@ -258,7 +258,7 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_enable);
void omap_dm_timer_disable(struct omap_dm_timer *timer)
{
pm_runtime_put(&timer->pdev->dev);
pm_runtime_put_sync(&timer->pdev->dev);
}
EXPORT_SYMBOL_GPL(omap_dm_timer_disable);

3
arch/arm/plat-omap/include/plat/cpu.h
View file

@ -372,7 +372,8 @@ IS_OMAP_TYPE(3430, 0x3430)
#define cpu_class_is_omap1() (cpu_is_omap7xx() || cpu_is_omap15xx() || \
cpu_is_omap16xx())
#define cpu_class_is_omap2() (cpu_is_omap24xx() || cpu_is_omap34xx() || \
cpu_is_omap44xx() || soc_is_omap54xx())
cpu_is_omap44xx() || soc_is_omap54xx() || \
soc_is_am33xx())
/* Various silicon revisions for omap2 */
#define OMAP242X_CLASS 0x24200024

9
arch/arm/plat-omap/include/plat/multi.h
View file

@ -108,4 +108,13 @@
# endif
#endif
#ifdef CONFIG_SOC_AM33XX
# ifdef OMAP_NAME
# undef MULTI_OMAP2
# define MULTI_OMAP2
# else
# define OMAP_NAME am33xx
# endif
#endif
#endif /* __PLAT_OMAP_MULTI_H */

4
arch/arm/plat-omap/include/plat/uncompress.h
View file

@ -110,7 +110,7 @@ static inline void flush(void)
_DEBUG_LL_ENTRY(mach, AM33XX_UART##p##_BASE, OMAP_PORT_SHIFT, \
AM33XXUART##p)
static inline void __arch_decomp_setup(unsigned long arch_id)
static inline void arch_decomp_setup(void)
{
int port = 0;
@ -198,8 +198,6 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
} while (0);
}
#define arch_decomp_setup() __arch_decomp_setup(arch_id)
/*
* nothing to do
*/

4
drivers/cpufreq/omap-cpufreq.c
View file

@ -218,7 +218,7 @@ static int __cpuinit omap_cpu_init(struct cpufreq_policy *policy)
policy->cur = policy->min = policy->max = omap_getspeed(policy->cpu);
if (atomic_inc_return(&freq_table_users) == 1)
if (!freq_table)
result = opp_init_cpufreq_table(mpu_dev, &freq_table);
if (result) {
@ -227,6 +227,8 @@ static int __cpuinit omap_cpu_init(struct cpufreq_policy *policy)
goto fail_ck;
}
atomic_inc_return(&freq_table_users);
result = cpufreq_frequency_table_cpuinfo(policy, freq_table);
if (result)
goto fail_table;