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[MIPS] Remove obsolete isa_slot_offset

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The isa_slot_offset variable and its __ISA_IO_base macro is not used
anywhere anymore.  It does not look like a decent interface per today's
standards either.  Remove both including all places of initialization.

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Maciej W. Rozycki 2008-06-09 17:19:53 +01:00 committed by Ralf Baechle
parent cb11dfa024
commit c88a8b4ab0
6 changed files with 0 additions and 31 deletions
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1
arch/mips/jazz/setup.c
View file

@ -79,7 +79,6 @@ void __init plat_mem_setup(void)
if (mips_machtype == MACH_MIPS_MAGNUM_4000)
EISA_bus = 1;
#endif
isa_slot_offset = 0xe3000000;
/* request I/O space for devices used on all i[345]86 PCs */
for (i = 0; i < ARRAY_SIZE(jazz_io_resources); i++)

7
arch/mips/kernel/setup.c
View file

@ -68,13 +68,6 @@ static char command_line[CL_SIZE];
const unsigned long mips_io_port_base __read_mostly = -1;
EXPORT_SYMBOL(mips_io_port_base);
/*
* isa_slot_offset is the address where E(ISA) busaddress 0 is mapped
* for the processor.
*/
unsigned long isa_slot_offset;
EXPORT_SYMBOL(isa_slot_offset);
static struct resource code_resource = { .name = "Kernel code", };
static struct resource data_resource = { .name = "Kernel data", };

2
arch/mips/pci/pci-bcm1480.c
View file

@ -254,8 +254,6 @@ static int __init bcm1480_pcibios_init(void)
ioremap(A_BCM1480_PHYS_PCI_IO_MATCH_BYTES, 65536);
bcm1480_controller.io_map_base -= bcm1480_controller.io_offset;
set_io_port_base(bcm1480_controller.io_map_base);
isa_slot_offset = (unsigned long)
ioremap(A_BCM1480_PHYS_PCI_MEM_MATCH_BYTES, 1024*1024);
register_pci_controller(&bcm1480_controller);

3
arch/mips/pci/pci-sb1250.c
View file

@ -254,9 +254,6 @@ static int __init sb1250_pcibios_init(void)
* works correctly with most of Linux's drivers.
* XXX ehs: Should this happen in PCI Device mode?
*/
isa_slot_offset = (unsigned long)
ioremap(A_PHYS_LDTPCI_IO_MATCH_BYTES_32, 1024 * 1024);
io_map_base = ioremap(A_PHYS_LDTPCI_IO_MATCH_BYTES, 1024 * 1024);
sb1250_controller.io_map_base = io_map_base;
set_io_port_base((unsigned long)io_map_base);

1
arch/mips/sni/setup.c
View file

@ -116,7 +116,6 @@ void __init plat_mem_setup(void)
/*
* Setup (E)ISA I/O memory access stuff
*/
isa_slot_offset = CKSEG1ADDR(0xb0000000);
#ifdef CONFIG_EISA
EISA_bus = 1;
#endif

17
include/asm-mips/io.h
View file

@ -160,13 +160,6 @@ static inline void * isa_bus_to_virt(unsigned long address)
#define virt_to_bus virt_to_phys
#define bus_to_virt phys_to_virt
/*
* isa_slot_offset is the address where E(ISA) busaddress 0 is mapped
* for the processor. This implies the assumption that there is only
* one of these busses.
*/
extern unsigned long isa_slot_offset;
/*
* Change "struct page" to physical address.
*/
@ -527,16 +520,6 @@ static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int
memcpy((void __force *) dst, src, count);
}
/*
* ISA space is 'always mapped' on currently supported MIPS systems, no need
* to explicitly ioremap() it. The fact that the ISA IO space is mapped
* to PAGE_OFFSET is pure coincidence - it does not mean ISA values
* are physical addresses. The following constant pointer can be
* used as the IO-area pointer (it can be iounmapped as well, so the
* analogy with PCI is quite large):
*/
#define __ISA_IO_base ((char *)(isa_slot_offset))
/*
* The caches on some architectures aren't dma-coherent and have need to
* handle this in software. There are three types of operations that