scsi: ufs: Change HCI macro to actual bit position
Currently UFS HCI uses UFS_BIT() macro to get various bit position for the hardware registers status bits. Which makes code longer instead of shorter. This macro does not improve code readability as well. Lets re-write these macro definition with the actual bit position. Suggested-by: Bart Van Assche <Bart.VanAssche@wdc.com> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Reviewed-by: Bart Van Assche <bart.vanassche@wdc.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
This commit is contained in:
Alim Akhtar
Martin K. Petersen
parent
f6cab3452b
commit
cc81641a45
2 changed files with 42 additions and 38 deletions
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@ -546,13 +546,13 @@ struct ufs_hba {
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bool is_irq_enabled;
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/* Interrupt aggregation support is broken */
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#define UFSHCD_QUIRK_BROKEN_INTR_AGGR UFS_BIT(0)
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#define UFSHCD_QUIRK_BROKEN_INTR_AGGR 0x1
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/*
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* delay before each dme command is required as the unipro
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* layer has shown instabilities
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*/
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#define UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS UFS_BIT(1)
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#define UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS 0x2
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/*
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* If UFS host controller is having issue in processing LCC (Line
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@ -561,21 +561,21 @@ struct ufs_hba {
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* the LCC transmission on UFS device (by clearing TX_LCC_ENABLE
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* attribute of device to 0).
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*/
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#define UFSHCD_QUIRK_BROKEN_LCC UFS_BIT(2)
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#define UFSHCD_QUIRK_BROKEN_LCC 0x4
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/*
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* The attribute PA_RXHSUNTERMCAP specifies whether or not the
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* inbound Link supports unterminated line in HS mode. Setting this
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* attribute to 1 fixes moving to HS gear.
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*/
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#define UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP UFS_BIT(3)
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#define UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP 0x8
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/*
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* This quirk needs to be enabled if the host contoller only allows
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* accessing the peer dme attributes in AUTO mode (FAST AUTO or
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* SLOW AUTO).
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*/
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#define UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE UFS_BIT(4)
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#define UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE 0x10
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/*
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* This quirk needs to be enabled if the host contoller doesn't
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@ -583,13 +583,13 @@ struct ufs_hba {
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* is enabled, standard UFS host driver will call the vendor specific
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* ops (get_ufs_hci_version) to get the correct version.
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*/
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#define UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION UFS_BIT(5)
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#define UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION 0x20
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/*
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* This quirk needs to be enabled if the host contoller regards
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* resolution of the values of PRDTO and PRDTL in UTRD as byte.
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*/
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#define UFSHCD_QUIRK_PRDT_BYTE_GRAN UFS_BIT(7)
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#define UFSHCD_QUIRK_PRDT_BYTE_GRAN 0x80
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unsigned int quirks; /* Deviations from standard UFSHCI spec. */
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@ -121,20 +121,23 @@ enum {
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#define UFS_BIT(x) (1L << (x))
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#define UTP_TRANSFER_REQ_COMPL UFS_BIT(0)
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#define UIC_DME_END_PT_RESET UFS_BIT(1)
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#define UIC_ERROR UFS_BIT(2)
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#define UIC_TEST_MODE UFS_BIT(3)
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#define UIC_POWER_MODE UFS_BIT(4)
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#define UIC_HIBERNATE_EXIT UFS_BIT(5)
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#define UIC_HIBERNATE_ENTER UFS_BIT(6)
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#define UIC_LINK_LOST UFS_BIT(7)
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#define UIC_LINK_STARTUP UFS_BIT(8)
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#define UTP_TASK_REQ_COMPL UFS_BIT(9)
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#define UIC_COMMAND_COMPL UFS_BIT(10)
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#define DEVICE_FATAL_ERROR UFS_BIT(11)
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#define CONTROLLER_FATAL_ERROR UFS_BIT(16)
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#define SYSTEM_BUS_FATAL_ERROR UFS_BIT(17)
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/*
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* IS - Interrupt Status - 20h
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*/
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#define UTP_TRANSFER_REQ_COMPL 0x1
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#define UIC_DME_END_PT_RESET 0x2
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#define UIC_ERROR 0x4
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#define UIC_TEST_MODE 0x8
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#define UIC_POWER_MODE 0x10
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#define UIC_HIBERNATE_EXIT 0x20
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#define UIC_HIBERNATE_ENTER 0x40
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#define UIC_LINK_LOST 0x80
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#define UIC_LINK_STARTUP 0x100
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#define UTP_TASK_REQ_COMPL 0x200
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#define UIC_COMMAND_COMPL 0x400
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#define DEVICE_FATAL_ERROR 0x800
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#define CONTROLLER_FATAL_ERROR 0x10000
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#define SYSTEM_BUS_FATAL_ERROR 0x20000
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#define UFSHCD_UIC_PWR_MASK (UIC_HIBERNATE_ENTER |\
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UIC_HIBERNATE_EXIT |\
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@ -152,10 +155,10 @@ enum {
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SYSTEM_BUS_FATAL_ERROR)
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/* HCS - Host Controller Status 30h */
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#define DEVICE_PRESENT UFS_BIT(0)
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#define UTP_TRANSFER_REQ_LIST_READY UFS_BIT(1)
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#define UTP_TASK_REQ_LIST_READY UFS_BIT(2)
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#define UIC_COMMAND_READY UFS_BIT(3)
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#define DEVICE_PRESENT 0x1
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#define UTP_TRANSFER_REQ_LIST_READY 0x2
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#define UTP_TASK_REQ_LIST_READY 0x4
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#define UIC_COMMAND_READY 0x8
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#define HOST_ERROR_INDICATOR UFS_BIT(4)
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#define DEVICE_ERROR_INDICATOR UFS_BIT(5)
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#define UIC_POWER_MODE_CHANGE_REQ_STATUS_MASK UFS_MASK(0x7, 8)
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@ -174,46 +177,47 @@ enum {
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};
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/* HCE - Host Controller Enable 34h */
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#define CONTROLLER_ENABLE UFS_BIT(0)
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#define CONTROLLER_ENABLE 0x1
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#define CONTROLLER_DISABLE 0x0
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#define CRYPTO_GENERAL_ENABLE UFS_BIT(1)
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#define CRYPTO_GENERAL_ENABLE 0x2
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/* UECPA - Host UIC Error Code PHY Adapter Layer 38h */
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#define UIC_PHY_ADAPTER_LAYER_ERROR UFS_BIT(31)
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#define UIC_PHY_ADAPTER_LAYER_ERROR 0x80000000
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#define UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK 0x1F
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#define UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK 0xF
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/* UECDL - Host UIC Error Code Data Link Layer 3Ch */
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#define UIC_DATA_LINK_LAYER_ERROR UFS_BIT(31)
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#define UIC_DATA_LINK_LAYER_ERROR 0x80000000
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#define UIC_DATA_LINK_LAYER_ERROR_CODE_MASK 0x7FFF
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#define UIC_DATA_LINK_LAYER_ERROR_PA_INIT 0x2000
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#define UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED 0x0001
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#define UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT 0x0002
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/* UECN - Host UIC Error Code Network Layer 40h */
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#define UIC_NETWORK_LAYER_ERROR UFS_BIT(31)
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#define UIC_NETWORK_LAYER_ERROR 0x80000000
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#define UIC_NETWORK_LAYER_ERROR_CODE_MASK 0x7
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/* UECT - Host UIC Error Code Transport Layer 44h */
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#define UIC_TRANSPORT_LAYER_ERROR UFS_BIT(31)
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#define UIC_TRANSPORT_LAYER_ERROR 0x80000000
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#define UIC_TRANSPORT_LAYER_ERROR_CODE_MASK 0x7F
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/* UECDME - Host UIC Error Code DME 48h */
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#define UIC_DME_ERROR UFS_BIT(31)
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#define UIC_DME_ERROR 0x80000000
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#define UIC_DME_ERROR_CODE_MASK 0x1
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/* UTRIACR - Interrupt Aggregation control register - 0x4Ch */
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#define INT_AGGR_TIMEOUT_VAL_MASK 0xFF
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#define INT_AGGR_COUNTER_THRESHOLD_MASK UFS_MASK(0x1F, 8)
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#define INT_AGGR_COUNTER_AND_TIMER_RESET UFS_BIT(16)
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#define INT_AGGR_STATUS_BIT UFS_BIT(20)
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#define INT_AGGR_PARAM_WRITE UFS_BIT(24)
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#define INT_AGGR_ENABLE UFS_BIT(31)
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#define INT_AGGR_COUNTER_AND_TIMER_RESET 0x10000
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#define INT_AGGR_STATUS_BIT 0x100000
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#define INT_AGGR_PARAM_WRITE 0x1000000
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#define INT_AGGR_ENABLE 0x80000000
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/* UTRLRSR - UTP Transfer Request Run-Stop Register 60h */
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#define UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT UFS_BIT(0)
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#define UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT 0x1
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/* UTMRLRSR - UTP Task Management Request Run-Stop Register 80h */
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#define UTP_TASK_REQ_LIST_RUN_STOP_BIT UFS_BIT(0)
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#define UTP_TASK_REQ_LIST_RUN_STOP_BIT 0x1
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/* UICCMD - UIC Command */
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#define COMMAND_OPCODE_MASK 0xFF
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