PCI: add more checking to ICH region quirks
Per ICH4 and ICH6 specs, ACPI and GPIO regions are valid iff ACPI_EN and GPIO_EN bits are set to 1. Add checks for these bits into the quirks prior to the region creation. While at it, name the constants by macros. Signed-off-by: Jiri Slaby <jslaby@suse.cz> Cc: Bjorn Helgaas <bjorn.helgaas@hp.com> Cc: "David S. Miller" <davem@davemloft.net> Cc: Thomas Renninger <trenn@suse.de> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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1 changed files with 37 additions and 8 deletions
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@ -533,6 +533,17 @@ static void __devinit quirk_piix4_acpi(struct pci_dev *dev)
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi);
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#define ICH_PMBASE 0x40
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#define ICH_ACPI_CNTL 0x44
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#define ICH4_ACPI_EN 0x10
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#define ICH6_ACPI_EN 0x80
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#define ICH4_GPIOBASE 0x58
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#define ICH4_GPIO_CNTL 0x5c
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#define ICH4_GPIO_EN 0x10
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#define ICH6_GPIOBASE 0x48
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#define ICH6_GPIO_CNTL 0x4c
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#define ICH6_GPIO_EN 0x10
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/*
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/*
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* ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
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* ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
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* 0x40 (128 bytes of ACPI, GPIO & TCO registers)
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* 0x40 (128 bytes of ACPI, GPIO & TCO registers)
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@ -541,12 +552,21 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, qui
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static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev)
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static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev)
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{
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{
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u32 region;
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u32 region;
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u8 enable;
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pci_read_config_dword(dev, 0x40, ®ion);
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pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
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quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH4 ACPI/GPIO/TCO");
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if (enable & ICH4_ACPI_EN) {
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pci_read_config_dword(dev, ICH_PMBASE, ®ion);
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quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES,
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"ICH4 ACPI/GPIO/TCO");
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}
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pci_read_config_dword(dev, 0x58, ®ion);
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pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable);
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quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH4 GPIO");
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if (enable & ICH4_GPIO_EN) {
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pci_read_config_dword(dev, ICH4_GPIOBASE, ®ion);
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quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES + 1,
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"ICH4 GPIO");
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}
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}
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi);
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@ -562,12 +582,21 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, qui
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static void __devinit ich6_lpc_acpi_gpio(struct pci_dev *dev)
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static void __devinit ich6_lpc_acpi_gpio(struct pci_dev *dev)
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{
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{
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u32 region;
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u32 region;
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u8 enable;
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pci_read_config_dword(dev, 0x40, ®ion);
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pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
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quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH6 ACPI/GPIO/TCO");
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if (enable & ICH6_ACPI_EN) {
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pci_read_config_dword(dev, ICH_PMBASE, ®ion);
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quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES,
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"ICH6 ACPI/GPIO/TCO");
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}
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pci_read_config_dword(dev, 0x48, ®ion);
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pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable);
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quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH6 GPIO");
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if (enable & ICH4_GPIO_EN) {
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pci_read_config_dword(dev, ICH6_GPIOBASE, ®ion);
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quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES + 1,
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"ICH6 GPIO");
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}
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}
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}
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static void __devinit ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name, int dynsize)
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static void __devinit ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name, int dynsize)
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