amd64_edac: add error decoding logic
Borislav: - fold amd64_error_info_valid() into its only user - fix/cleanup comments - fix function return value patterns - cleanup debug calls Reviewed-by: Mauro Carvalho Chehab <mchehab@redhat.com> Signed-off-by: Doug Thompson <dougthompson@xmission.com> Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
This commit is contained in:
Doug Thompson
Borislav Petkov
parent
b1289d6f9d
commit
d27bf6fa36
1 changed files with 425 additions and 0 deletions
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@ -2031,3 +2031,428 @@ static int get_channel_from_ecc_syndrome(unsigned short syndrome)
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debugf0("syndrome(%x) not found\n", syndrome);
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return -1;
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}
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/*
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* Check for valid error in the NB Status High register. If so, proceed to read
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* NB Status Low, NB Address Low and NB Address High registers and store data
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* into error structure.
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*
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* Returns:
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* - 1: if hardware regs contains valid error info
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* - 0: if no valid error is indicated
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*/
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static int amd64_get_error_info_regs(struct mem_ctl_info *mci,
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struct amd64_error_info_regs *regs)
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{
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struct amd64_pvt *pvt;
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struct pci_dev *misc_f3_ctl;
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int err = 0;
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pvt = mci->pvt_info;
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misc_f3_ctl = pvt->misc_f3_ctl;
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err = pci_read_config_dword(misc_f3_ctl, K8_NBSH, ®s->nbsh);
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if (err)
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goto err_reg;
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if (!(regs->nbsh & K8_NBSH_VALID_BIT))
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return 0;
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/* valid error, read remaining error information registers */
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err = pci_read_config_dword(misc_f3_ctl, K8_NBSL, ®s->nbsl);
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if (err)
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goto err_reg;
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err = pci_read_config_dword(misc_f3_ctl, K8_NBEAL, ®s->nbeal);
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if (err)
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goto err_reg;
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err = pci_read_config_dword(misc_f3_ctl, K8_NBEAH, ®s->nbeah);
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if (err)
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goto err_reg;
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err = pci_read_config_dword(misc_f3_ctl, K8_NBCFG, ®s->nbcfg);
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if (err)
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goto err_reg;
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return 1;
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err_reg:
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debugf0("Reading error info register failed\n");
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return 0;
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}
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/*
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* This function is called to retrieve the error data from hardware and store it
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* in the info structure.
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*
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* Returns:
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* - 1: if a valid error is found
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* - 0: if no error is found
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*/
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static int amd64_get_error_info(struct mem_ctl_info *mci,
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struct amd64_error_info_regs *info)
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{
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struct amd64_pvt *pvt;
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struct amd64_error_info_regs regs;
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pvt = mci->pvt_info;
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if (!amd64_get_error_info_regs(mci, info))
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return 0;
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/*
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* Here's the problem with the K8's EDAC reporting: There are four
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* registers which report pieces of error information. They are shared
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* between CEs and UEs. Furthermore, contrary to what is stated in the
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* BKDG, the overflow bit is never used! Every error always updates the
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* reporting registers.
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*
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* Can you see the race condition? All four error reporting registers
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* must be read before a new error updates them! There is no way to read
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* all four registers atomically. The best than can be done is to detect
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* that a race has occured and then report the error without any kind of
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* precision.
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*
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* What is still positive is that errors are still reported and thus
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* problems can still be detected - just not localized because the
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* syndrome and address are spread out across registers.
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*
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* Grrrrr!!!!! Here's hoping that AMD fixes this in some future K8 rev.
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* UEs and CEs should have separate register sets with proper overflow
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* bits that are used! At very least the problem can be fixed by
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* honoring the ErrValid bit in 'nbsh' and not updating registers - just
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* set the overflow bit - unless the current error is CE and the new
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* error is UE which would be the only situation for overwriting the
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* current values.
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*/
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regs = *info;
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/* Use info from the second read - most current */
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if (unlikely(!amd64_get_error_info_regs(mci, info)))
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return 0;
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/* clear the error bits in hardware */
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pci_write_bits32(pvt->misc_f3_ctl, K8_NBSH, 0, K8_NBSH_VALID_BIT);
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/* Check for the possible race condition */
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if ((regs.nbsh != info->nbsh) ||
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(regs.nbsl != info->nbsl) ||
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(regs.nbeah != info->nbeah) ||
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(regs.nbeal != info->nbeal)) {
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amd64_mc_printk(mci, KERN_WARNING,
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"hardware STATUS read access race condition "
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"detected!\n");
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return 0;
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}
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return 1;
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}
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static inline void amd64_decode_gart_tlb_error(struct mem_ctl_info *mci,
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struct amd64_error_info_regs *info)
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{
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u32 err_code;
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u32 ec_tt; /* error code transaction type (2b) */
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u32 ec_ll; /* error code cache level (2b) */
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err_code = EXTRACT_ERROR_CODE(info->nbsl);
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ec_ll = EXTRACT_LL_CODE(err_code);
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ec_tt = EXTRACT_TT_CODE(err_code);
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amd64_mc_printk(mci, KERN_ERR,
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"GART TLB event: transaction type(%s), "
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"cache level(%s)\n", tt_msgs[ec_tt], ll_msgs[ec_ll]);
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}
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static inline void amd64_decode_mem_cache_error(struct mem_ctl_info *mci,
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struct amd64_error_info_regs *info)
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{
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u32 err_code;
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u32 ec_rrrr; /* error code memory transaction (4b) */
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u32 ec_tt; /* error code transaction type (2b) */
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u32 ec_ll; /* error code cache level (2b) */
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err_code = EXTRACT_ERROR_CODE(info->nbsl);
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ec_ll = EXTRACT_LL_CODE(err_code);
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ec_tt = EXTRACT_TT_CODE(err_code);
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ec_rrrr = EXTRACT_RRRR_CODE(err_code);
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amd64_mc_printk(mci, KERN_ERR,
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"cache hierarchy error: memory transaction type(%s), "
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"transaction type(%s), cache level(%s)\n",
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rrrr_msgs[ec_rrrr], tt_msgs[ec_tt], ll_msgs[ec_ll]);
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}
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/*
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* Handle any Correctable Errors (CEs) that have occurred. Check for valid ERROR
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* ADDRESS and process.
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*/
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static void amd64_handle_ce(struct mem_ctl_info *mci,
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struct amd64_error_info_regs *info)
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{
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struct amd64_pvt *pvt = mci->pvt_info;
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u64 SystemAddress;
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/* Ensure that the Error Address is VALID */
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if ((info->nbsh & K8_NBSH_VALID_ERROR_ADDR) == 0) {
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amd64_mc_printk(mci, KERN_ERR,
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"HW has no ERROR_ADDRESS available\n");
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edac_mc_handle_ce_no_info(mci, EDAC_MOD_STR);
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return;
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}
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SystemAddress = extract_error_address(mci, info);
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amd64_mc_printk(mci, KERN_ERR,
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"CE ERROR_ADDRESS= 0x%llx\n", SystemAddress);
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pvt->ops->map_sysaddr_to_csrow(mci, info, SystemAddress);
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}
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/* Handle any Un-correctable Errors (UEs) */
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static void amd64_handle_ue(struct mem_ctl_info *mci,
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struct amd64_error_info_regs *info)
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{
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int csrow;
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u64 SystemAddress;
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u32 page, offset;
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struct mem_ctl_info *log_mci, *src_mci = NULL;
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log_mci = mci;
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if ((info->nbsh & K8_NBSH_VALID_ERROR_ADDR) == 0) {
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amd64_mc_printk(mci, KERN_CRIT,
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"HW has no ERROR_ADDRESS available\n");
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edac_mc_handle_ue_no_info(log_mci, EDAC_MOD_STR);
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return;
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}
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SystemAddress = extract_error_address(mci, info);
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/*
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* Find out which node the error address belongs to. This may be
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* different from the node that detected the error.
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*/
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src_mci = find_mc_by_sys_addr(mci, SystemAddress);
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if (!src_mci) {
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amd64_mc_printk(mci, KERN_CRIT,
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"ERROR ADDRESS (0x%lx) value NOT mapped to a MC\n",
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(unsigned long)SystemAddress);
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edac_mc_handle_ue_no_info(log_mci, EDAC_MOD_STR);
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return;
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}
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log_mci = src_mci;
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csrow = sys_addr_to_csrow(log_mci, SystemAddress);
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if (csrow < 0) {
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amd64_mc_printk(mci, KERN_CRIT,
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"ERROR_ADDRESS (0x%lx) value NOT mapped to 'csrow'\n",
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(unsigned long)SystemAddress);
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edac_mc_handle_ue_no_info(log_mci, EDAC_MOD_STR);
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} else {
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error_address_to_page_and_offset(SystemAddress, &page, &offset);
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edac_mc_handle_ue(log_mci, page, offset, csrow, EDAC_MOD_STR);
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}
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}
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static void amd64_decode_bus_error(struct mem_ctl_info *mci,
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struct amd64_error_info_regs *info)
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{
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u32 err_code, ext_ec;
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u32 ec_pp; /* error code participating processor (2p) */
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u32 ec_to; /* error code timed out (1b) */
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u32 ec_rrrr; /* error code memory transaction (4b) */
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u32 ec_ii; /* error code memory or I/O (2b) */
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u32 ec_ll; /* error code cache level (2b) */
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ext_ec = EXTRACT_EXT_ERROR_CODE(info->nbsl);
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err_code = EXTRACT_ERROR_CODE(info->nbsl);
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ec_ll = EXTRACT_LL_CODE(err_code);
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ec_ii = EXTRACT_II_CODE(err_code);
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ec_rrrr = EXTRACT_RRRR_CODE(err_code);
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ec_to = EXTRACT_TO_CODE(err_code);
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ec_pp = EXTRACT_PP_CODE(err_code);
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amd64_mc_printk(mci, KERN_ERR,
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"BUS ERROR:\n"
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" time-out(%s) mem or i/o(%s)\n"
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" participating processor(%s)\n"
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" memory transaction type(%s)\n"
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" cache level(%s) Error Found by: %s\n",
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to_msgs[ec_to],
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ii_msgs[ec_ii],
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pp_msgs[ec_pp],
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rrrr_msgs[ec_rrrr],
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ll_msgs[ec_ll],
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(info->nbsh & K8_NBSH_ERR_SCRUBER) ?
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"Scrubber" : "Normal Operation");
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/* If this was an 'observed' error, early out */
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if (ec_pp == K8_NBSL_PP_OBS)
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return; /* We aren't the node involved */
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/* Parse out the extended error code for ECC events */
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switch (ext_ec) {
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/* F10 changed to one Extended ECC error code */
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case F10_NBSL_EXT_ERR_RES: /* Reserved field */
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case F10_NBSL_EXT_ERR_ECC: /* F10 ECC ext err code */
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break;
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default:
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amd64_mc_printk(mci, KERN_ERR, "NOT ECC: no special error "
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"handling for this error\n");
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return;
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}
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if (info->nbsh & K8_NBSH_CECC)
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amd64_handle_ce(mci, info);
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else if (info->nbsh & K8_NBSH_UECC)
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amd64_handle_ue(mci, info);
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/*
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* If main error is CE then overflow must be CE. If main error is UE
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* then overflow is unknown. We'll call the overflow a CE - if
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* panic_on_ue is set then we're already panic'ed and won't arrive
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* here. Else, then apparently someone doesn't think that UE's are
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* catastrophic.
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*/
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if (info->nbsh & K8_NBSH_OVERFLOW)
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edac_mc_handle_ce_no_info(mci, EDAC_MOD_STR
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"Error Overflow set");
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}
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int amd64_process_error_info(struct mem_ctl_info *mci,
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struct amd64_error_info_regs *info,
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int handle_errors)
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{
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struct amd64_pvt *pvt;
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struct amd64_error_info_regs *regs;
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u32 err_code, ext_ec;
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int gart_tlb_error = 0;
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pvt = mci->pvt_info;
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/* If caller doesn't want us to process the error, return */
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if (!handle_errors)
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return 1;
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regs = info;
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debugf1("NorthBridge ERROR: mci(0x%p)\n", mci);
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debugf1(" MC node(%d) Error-Address(0x%.8x-%.8x)\n",
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pvt->mc_node_id, regs->nbeah, regs->nbeal);
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debugf1(" nbsh(0x%.8x) nbsl(0x%.8x)\n",
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regs->nbsh, regs->nbsl);
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debugf1(" Valid Error=%s Overflow=%s\n",
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(regs->nbsh & K8_NBSH_VALID_BIT) ? "True" : "False",
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(regs->nbsh & K8_NBSH_OVERFLOW) ? "True" : "False");
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debugf1(" Err Uncorrected=%s MCA Error Reporting=%s\n",
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(regs->nbsh & K8_NBSH_UNCORRECTED_ERR) ?
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"True" : "False",
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(regs->nbsh & K8_NBSH_ERR_ENABLE) ?
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"True" : "False");
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debugf1(" MiscErr Valid=%s ErrAddr Valid=%s PCC=%s\n",
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(regs->nbsh & K8_NBSH_MISC_ERR_VALID) ?
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"True" : "False",
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(regs->nbsh & K8_NBSH_VALID_ERROR_ADDR) ?
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"True" : "False",
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(regs->nbsh & K8_NBSH_PCC) ?
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"True" : "False");
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debugf1(" CECC=%s UECC=%s Found by Scruber=%s\n",
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(regs->nbsh & K8_NBSH_CECC) ?
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"True" : "False",
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(regs->nbsh & K8_NBSH_UECC) ?
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"True" : "False",
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(regs->nbsh & K8_NBSH_ERR_SCRUBER) ?
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"True" : "False");
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debugf1(" CORE0=%s CORE1=%s CORE2=%s CORE3=%s\n",
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(regs->nbsh & K8_NBSH_CORE0) ? "True" : "False",
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(regs->nbsh & K8_NBSH_CORE1) ? "True" : "False",
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(regs->nbsh & K8_NBSH_CORE2) ? "True" : "False",
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(regs->nbsh & K8_NBSH_CORE3) ? "True" : "False");
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err_code = EXTRACT_ERROR_CODE(regs->nbsl);
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/* Determine which error type:
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* 1) GART errors - non-fatal, developmental events
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* 2) MEMORY errors
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* 3) BUS errors
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* 4) Unknown error
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*/
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if (TEST_TLB_ERROR(err_code)) {
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/*
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* GART errors are intended to help graphics driver developers
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* to detect bad GART PTEs. It is recommended by AMD to disable
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* GART table walk error reporting by default[1] (currently
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* being disabled in mce_cpu_quirks()) and according to the
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* comment in mce_cpu_quirks(), such GART errors can be
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* incorrectly triggered. We may see these errors anyway and
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* unless requested by the user, they won't be reported.
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*
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* [1] section 13.10.1 on BIOS and Kernel Developers Guide for
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* AMD NPT family 0Fh processors
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*/
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if (report_gart_errors == 0)
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return 1;
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/*
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* Only if GART error reporting is requested should we generate
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* any logs.
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*/
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gart_tlb_error = 1;
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debugf1("GART TLB error\n");
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amd64_decode_gart_tlb_error(mci, info);
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} else if (TEST_MEM_ERROR(err_code)) {
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debugf1("Memory/Cache error\n");
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amd64_decode_mem_cache_error(mci, info);
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} else if (TEST_BUS_ERROR(err_code)) {
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debugf1("Bus (Link/DRAM) error\n");
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amd64_decode_bus_error(mci, info);
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} else {
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/* shouldn't reach here! */
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amd64_mc_printk(mci, KERN_WARNING,
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"%s(): unknown MCE error 0x%x\n", __func__,
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err_code);
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}
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ext_ec = EXTRACT_EXT_ERROR_CODE(regs->nbsl);
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amd64_mc_printk(mci, KERN_ERR,
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"ExtErr=(0x%x) %s\n", ext_ec, ext_msgs[ext_ec]);
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if (((ext_ec >= F10_NBSL_EXT_ERR_CRC &&
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ext_ec <= F10_NBSL_EXT_ERR_TGT) ||
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(ext_ec == F10_NBSL_EXT_ERR_RMW)) &&
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EXTRACT_LDT_LINK(info->nbsh)) {
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amd64_mc_printk(mci, KERN_ERR,
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"Error on hypertransport link: %s\n",
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htlink_msgs[
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EXTRACT_LDT_LINK(info->nbsh)]);
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}
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/*
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* Check the UE bit of the NB status high register, if set generate some
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* logs. If NOT a GART error, then process the event as a NO-INFO event.
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* If it was a GART error, skip that process.
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*/
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if (regs->nbsh & K8_NBSH_UNCORRECTED_ERR) {
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amd64_mc_printk(mci, KERN_CRIT, "uncorrected error\n");
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if (!gart_tlb_error)
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edac_mc_handle_ue_no_info(mci, "UE bit is set\n");
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}
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|
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if (regs->nbsh & K8_NBSH_PCC)
|
||||
amd64_mc_printk(mci, KERN_CRIT,
|
||||
"PCC (processor context corrupt) set\n");
|
||||
|
||||
return 1;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(amd64_process_error_info);
|
||||
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue