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serial: sh-sci: Generalize port pin initialization.

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Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Paul Mundt 2008-12-16 20:07:27 +09:00
parent d830fa4584
commit d5701647f1
2 changed files with 43 additions and 114 deletions
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145
drivers/serial/sh-sci.c
View file

@ -64,10 +64,6 @@ struct sci_port {
/* Port IRQs: ERI, RXI, TXI, BRI (optional) */ /* Port IRQs: ERI, RXI, TXI, BRI (optional) */
unsigned int irqs[SCIx_NR_IRQS]; unsigned int irqs[SCIx_NR_IRQS];
/* Port pin configuration */
void (*init_pins)(struct uart_port *port,
unsigned int cflag);
/* Port enable callback */ /* Port enable callback */
void (*enable)(struct uart_port *port); void (*enable)(struct uart_port *port);
@ -172,7 +168,7 @@ static inline void h8300_sci_disable(struct uart_port *port)
#endif #endif
#if defined(__H8300H__) || defined(__H8300S__) #if defined(__H8300H__) || defined(__H8300S__)
static void sci_init_pins_sci(struct uart_port *port, unsigned int cflag) static void sci_init_pins(struct uart_port *port, unsigned int cflag)
{ {
int ch = (port->mapbase - SMR0) >> 3; int ch = (port->mapbase - SMR0) >> 3;
@ -187,140 +183,99 @@ static void sci_init_pins_sci(struct uart_port *port, unsigned int cflag)
/* tx mark output*/ /* tx mark output*/
H8300_SCI_DR(ch) |= h8300_sci_pins[ch].tx; H8300_SCI_DR(ch) |= h8300_sci_pins[ch].tx;
} }
#else #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
#define sci_init_pins_sci NULL static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
#endif
#if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
static void sci_init_pins_irda(struct uart_port *port, unsigned int cflag)
{ {
unsigned int fcr_val = 0; if (port->mapbase == 0xA4400000) {
__raw_writew(__raw_readw(PACR) & 0xffc0, PACR);
if (cflag & CRTSCTS) __raw_writew(__raw_readw(PBCR) & 0x0fff, PBCR);
fcr_val |= SCFCR_MCE; } else if (port->mapbase == 0xA4410000)
__raw_writew(__raw_readw(PBCR) & 0xf003, PBCR);
sci_out(port, SCFCR, fcr_val);
}
#else
#define sci_init_pins_irda NULL
#endif
#if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
{
unsigned int fcr_val = 0;
set_sh771x_scif_pfc(port);
if (cflag & CRTSCTS)
fcr_val |= SCFCR_MCE;
sci_out(port, SCFCR, fcr_val);
} }
#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7721) #elif defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7721)
static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag) static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
{ {
unsigned int fcr_val = 0;
unsigned short data; unsigned short data;
if (cflag & CRTSCTS) { if (cflag & CRTSCTS) {
/* enable RTS/CTS */ /* enable RTS/CTS */
if (port->mapbase == 0xa4430000) { /* SCIF0 */ if (port->mapbase == 0xa4430000) { /* SCIF0 */
/* Clear PTCR bit 9-2; enable all scif pins but sck */ /* Clear PTCR bit 9-2; enable all scif pins but sck */
data = ctrl_inw(PORT_PTCR); data = __raw_readw(PORT_PTCR);
ctrl_outw((data & 0xfc03), PORT_PTCR); __raw_writew((data & 0xfc03), PORT_PTCR);
} else if (port->mapbase == 0xa4438000) { /* SCIF1 */ } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
/* Clear PVCR bit 9-2 */ /* Clear PVCR bit 9-2 */
data = ctrl_inw(PORT_PVCR); data = __raw_readw(PORT_PVCR);
ctrl_outw((data & 0xfc03), PORT_PVCR); __raw_writew((data & 0xfc03), PORT_PVCR);
} }
fcr_val |= SCFCR_MCE;
} else { } else {
if (port->mapbase == 0xa4430000) { /* SCIF0 */ if (port->mapbase == 0xa4430000) { /* SCIF0 */
/* Clear PTCR bit 5-2; enable only tx and rx */ /* Clear PTCR bit 5-2; enable only tx and rx */
data = ctrl_inw(PORT_PTCR); data = __raw_readw(PORT_PTCR);
ctrl_outw((data & 0xffc3), PORT_PTCR); __raw_writew((data & 0xffc3), PORT_PTCR);
} else if (port->mapbase == 0xa4438000) { /* SCIF1 */ } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
/* Clear PVCR bit 5-2 */ /* Clear PVCR bit 5-2 */
data = ctrl_inw(PORT_PVCR); data = __raw_readw(PORT_PVCR);
ctrl_outw((data & 0xffc3), PORT_PVCR); __raw_writew((data & 0xffc3), PORT_PVCR);
} }
} }
sci_out(port, SCFCR, fcr_val);
} }
#elif defined(CONFIG_CPU_SH3) #elif defined(CONFIG_CPU_SH3)
/* For SH7705, SH7706, SH7707, SH7709, SH7709A, SH7729 */ /* For SH7705, SH7706, SH7707, SH7709, SH7709A, SH7729 */
static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag) static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
{ {
unsigned int fcr_val = 0;
unsigned short data; unsigned short data;
/* We need to set SCPCR to enable RTS/CTS */ /* We need to set SCPCR to enable RTS/CTS */
data = ctrl_inw(SCPCR); data = __raw_readw(SCPCR);
/* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/ /* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/
ctrl_outw(data & 0x0fcf, SCPCR); __raw_writew(data & 0x0fcf, SCPCR);
if (cflag & CRTSCTS) if (!(cflag & CRTSCTS)) {
fcr_val |= SCFCR_MCE;
else {
/* We need to set SCPCR to enable RTS/CTS */ /* We need to set SCPCR to enable RTS/CTS */
data = ctrl_inw(SCPCR); data = __raw_readw(SCPCR);
/* Clear out SCP7MD1,0, SCP4MD1,0, /* Clear out SCP7MD1,0, SCP4MD1,0,
Set SCP6MD1,0 = {01} (output) */ Set SCP6MD1,0 = {01} (output) */
ctrl_outw((data & 0x0fcf) | 0x1000, SCPCR); __raw_writew((data & 0x0fcf) | 0x1000, SCPCR);
data = ctrl_inb(SCPDR); data = ctrl_inb(SCPDR);
/* Set /RTS2 (bit6) = 0 */ /* Set /RTS2 (bit6) = 0 */
ctrl_outb(data & 0xbf, SCPDR); ctrl_outb(data & 0xbf, SCPDR);
} }
sci_out(port, SCFCR, fcr_val);
} }
#elif defined(CONFIG_CPU_SUBTYPE_SH7722) #elif defined(CONFIG_CPU_SUBTYPE_SH7722)
static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag) static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
{ {
unsigned int fcr_val = 0;
unsigned short data; unsigned short data;
if (port->mapbase == 0xffe00000) { if (port->mapbase == 0xffe00000) {
data = ctrl_inw(PSCR); data = __raw_readw(PSCR);
data &= ~0x03cf; data &= ~0x03cf;
if (cflag & CRTSCTS) if (!(cflag & CRTSCTS))
fcr_val |= SCFCR_MCE;
else
data |= 0x0340; data |= 0x0340;
ctrl_outw(data, PSCR); __raw_writew(data, PSCR);
} }
/* SCIF1 and SCIF2 should be setup by board code */
sci_out(port, SCFCR, fcr_val);
} }
#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
{
/* Nothing to do here.. */
sci_out(port, SCFCR, 0);
}
#else
/* For SH7750 */
static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
{
unsigned int fcr_val = 0;
if (cflag & CRTSCTS) {
fcr_val |= SCFCR_MCE;
} else {
#if defined(CONFIG_CPU_SUBTYPE_SH7343) || defined(CONFIG_CPU_SUBTYPE_SH7366)
/* Nothing */
#elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \ #elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
defined(CONFIG_CPU_SUBTYPE_SH7780) || \ defined(CONFIG_CPU_SUBTYPE_SH7780) || \
defined(CONFIG_CPU_SUBTYPE_SH7785) || \ defined(CONFIG_CPU_SUBTYPE_SH7785) || \
defined(CONFIG_CPU_SUBTYPE_SHX3) defined(CONFIG_CPU_SUBTYPE_SHX3)
ctrl_outw(0x0080, SCSPTR0); /* Set RTS = 1 */ static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
{
if (!(cflag & CRTSCTS))
__raw_writew(0x0080, SCSPTR0); /* Set RTS = 1 */
}
#elif defined(CONFIG_CPU_SH4)
static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
{
if (!(cflag & CRTSCTS))
__raw_writew(0x0080, SCSPTR2); /* Set RTS = 1 */
}
#else #else
ctrl_outw(0x0080, SCSPTR2); /* Set RTS = 1 */ static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
#endif {
} /* Nothing to do */
sci_out(port, SCFCR, fcr_val);
} }
#endif #endif
@ -941,7 +896,6 @@ static void sci_shutdown(struct uart_port *port)
static void sci_set_termios(struct uart_port *port, struct ktermios *termios, static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
struct ktermios *old) struct ktermios *old)
{ {
struct sci_port *s = &sci_ports[port->line];
unsigned int status, baud, smr_val; unsigned int status, baud, smr_val;
int t = -1; int t = -1;
@ -983,8 +937,8 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */ udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
} }
if (likely(s->init_pins)) sci_init_pins(port, termios->c_cflag);
s->init_pins(port, termios->c_cflag); sci_out(port, SCFCR, (termios->c_cflag & CRTSCTS) ? SCFCR_MCE : 0);
sci_out(port, SCSCR, SCSCR_INIT(port)); sci_out(port, SCSCR, SCSCR_INIT(port));
@ -1025,19 +979,6 @@ static void sci_config_port(struct uart_port *port, int flags)
port->type = s->type; port->type = s->type;
switch (port->type) {
case PORT_SCI:
s->init_pins = sci_init_pins_sci;
break;
case PORT_SCIF:
case PORT_SCIFA:
s->init_pins = sci_init_pins_scif;
break;
case PORT_IRDA:
s->init_pins = sci_init_pins_irda;
break;
}
if (port->flags & UPF_IOREMAP && !port->membase) { if (port->flags & UPF_IOREMAP && !port->membase) {
#if defined(CONFIG_SUPERH64) #if defined(CONFIG_SUPERH64)
port->mapbase = onchip_remap(SCIF_ADDR_SH5, 1024, "SCIF"); port->mapbase = onchip_remap(SCIF_ADDR_SH5, 1024, "SCIF");

12
drivers/serial/sh-sci.h
View file

@ -507,18 +507,6 @@ static inline int sci_rxd_in(struct uart_port *port)
{ {
return sci_in(port,SCxSR)&0x0010 ? 1 : 0; return sci_in(port,SCxSR)&0x0010 ? 1 : 0;
} }
static inline void set_sh771x_scif_pfc(struct uart_port *port)
{
if (port->mapbase == 0xA4400000){
ctrl_outw(ctrl_inw(PACR)&0xffc0,PACR);
ctrl_outw(ctrl_inw(PBCR)&0x0fff,PBCR);
return;
}
if (port->mapbase == 0xA4410000){
ctrl_outw(ctrl_inw(PBCR)&0xf003,PBCR);
return;
}
}
#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \ #elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \
defined(CONFIG_CPU_SUBTYPE_SH7721) defined(CONFIG_CPU_SUBTYPE_SH7721)
static inline int sci_rxd_in(struct uart_port *port) static inline int sci_rxd_in(struct uart_port *port)