dmaengine: dw: define DW_DMA_MAX_NR_MASTERS
Instead of using magic number in the code the patch provides DW_DMA_MAX_NR_MASTERS constant. While here, restrict the reading of data width array by amount of the actual number of AHB masters. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
This commit is contained in:
parent
cfd8fef322
commit
d8ded50f8b
8 changed files with 13 additions and 10 deletions
|
@ -38,7 +38,7 @@ Example:
|
|||
chan_allocation_order = <1>;
|
||||
chan_priority = <1>;
|
||||
block_size = <0xfff>;
|
||||
data_width = <3 3 0 0>;
|
||||
data_width = <3 3>;
|
||||
};
|
||||
|
||||
DMA clients connected to the Designware DMA controller must use the format
|
||||
|
|
|
@ -112,7 +112,7 @@
|
|||
chan_allocation_order = <0>;
|
||||
chan_priority = <1>;
|
||||
block_size = <0x7ff>;
|
||||
data_width = <2 0 0 0>;
|
||||
data_width = <2>;
|
||||
clocks = <&ahb_clk>;
|
||||
clock-names = "hclk";
|
||||
};
|
||||
|
|
|
@ -117,7 +117,7 @@
|
|||
chan_priority = <1>;
|
||||
block_size = <0xfff>;
|
||||
dma-masters = <2>;
|
||||
data_width = <3 3 0 0>;
|
||||
data_width = <3 3>;
|
||||
};
|
||||
|
||||
dma@eb000000 {
|
||||
|
@ -133,7 +133,7 @@
|
|||
chan_allocation_order = <1>;
|
||||
chan_priority = <1>;
|
||||
block_size = <0xfff>;
|
||||
data_width = <3 3 0 0>;
|
||||
data_width = <3 3>;
|
||||
};
|
||||
|
||||
fsmc: flash@b0000000 {
|
||||
|
|
|
@ -607,7 +607,7 @@ static struct dw_dma_platform_data dw_dmac0_data = {
|
|||
.nr_channels = 3,
|
||||
.block_size = 4095U,
|
||||
.nr_masters = 2,
|
||||
.data_width = { 2, 2, 0, 0 },
|
||||
.data_width = { 2, 2 },
|
||||
};
|
||||
|
||||
static struct resource dw_dmac0_resource[] = {
|
||||
|
|
|
@ -1562,7 +1562,8 @@ int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata)
|
|||
}
|
||||
} else {
|
||||
dw->nr_masters = pdata->nr_masters;
|
||||
memcpy(dw->data_width, pdata->data_width, 4);
|
||||
for (i = 0; i < dw->nr_masters; i++)
|
||||
dw->data_width[i] = pdata->data_width[i];
|
||||
}
|
||||
|
||||
/* Calculate all channel mask before DMA setup */
|
||||
|
|
|
@ -99,7 +99,7 @@ dw_dma_parse_dt(struct platform_device *pdev)
|
|||
{
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
struct dw_dma_platform_data *pdata;
|
||||
u32 tmp, arr[4];
|
||||
u32 tmp, arr[DW_DMA_MAX_NR_MASTERS];
|
||||
|
||||
if (!np) {
|
||||
dev_err(&pdev->dev, "Missing DT data\n");
|
||||
|
@ -126,7 +126,7 @@ dw_dma_parse_dt(struct platform_device *pdev)
|
|||
pdata->block_size = tmp;
|
||||
|
||||
if (!of_property_read_u32(np, "dma-masters", &tmp)) {
|
||||
if (tmp > 4)
|
||||
if (tmp > DW_DMA_MAX_NR_MASTERS)
|
||||
return NULL;
|
||||
|
||||
pdata->nr_masters = tmp;
|
||||
|
|
|
@ -285,7 +285,7 @@ struct dw_dma {
|
|||
|
||||
/* hardware configuration */
|
||||
unsigned char nr_masters;
|
||||
unsigned char data_width[4];
|
||||
unsigned char data_width[DW_DMA_MAX_NR_MASTERS];
|
||||
};
|
||||
|
||||
static inline struct dw_dma_regs __iomem *__dw_regs(struct dw_dma *dw)
|
||||
|
|
|
@ -13,6 +13,8 @@
|
|||
|
||||
#include <linux/device.h>
|
||||
|
||||
#define DW_DMA_MAX_NR_MASTERS 4
|
||||
|
||||
/**
|
||||
* struct dw_dma_slave - Controller-specific information about a slave
|
||||
*
|
||||
|
@ -53,7 +55,7 @@ struct dw_dma_platform_data {
|
|||
unsigned char chan_priority;
|
||||
unsigned short block_size;
|
||||
unsigned char nr_masters;
|
||||
unsigned char data_width[4];
|
||||
unsigned char data_width[DW_DMA_MAX_NR_MASTERS];
|
||||
};
|
||||
|
||||
#endif /* _PLATFORM_DATA_DMA_DW_H */
|
||||
|
|
Loading…
Reference in a new issue