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[ARM] 3893/1: pxa27x: Update UDCISR1 bit definitions

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This patch updates several bit definitions name in UDCISR1 register.

Signed-off-by: Stanley Cai <stanley.w.cai@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
stanley cai 2006-10-16 15:13:30 +01:00 committed by Russell King
parent eb8b0afc3a
commit d94cffe3d3
1 changed files with 5 additions and 6 deletions
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11
include/asm-arm/arch-pxa/pxa-regs.h
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@ -803,12 +803,11 @@
#define UDCISR0 __REG(0x4060000C) /* UDC Interrupt Status Register 0 */
#define UDCISR1 __REG(0x40600010) /* UDC Interrupt Status Register 1 */
#define UDCISR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
#define UDCISR1_IECC (1 << 31) /* IntEn - Configuration Change */
#define UDCISR1_IESOF (1 << 30) /* IntEn - Start of Frame */
#define UDCISR1_IERU (1 << 29) /* IntEn - Resume */
#define UDCISR1_IESU (1 << 28) /* IntEn - Suspend */
#define UDCISR1_IERS (1 << 27) /* IntEn - Reset */
#define UDCISR1_IRCC (1 << 31) /* IntReq - Configuration Change */
#define UDCISR1_IRSOF (1 << 30) /* IntReq - Start of Frame */
#define UDCISR1_IRRU (1 << 29) /* IntReq - Resume */
#define UDCISR1_IRSU (1 << 28) /* IntReq - Suspend */
#define UDCISR1_IRRS (1 << 27) /* IntReq - Reset */
#define UDCFNR __REG(0x40600014) /* UDC Frame Number Register */
#define UDCOTGICR __REG(0x40600018) /* UDC On-The-Go interrupt control */