ASoC: Add EQ and filter to max98095 CODEC driver
This patch adds the equalizer and biquad filter controls. Signed-off-by: Peter Hsiang <peter.hsiang@maxim-ic.com> Acked-by: Liam Girdwood <lrg@ti.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
This commit is contained in:
Peter Hsiang
Mark Brown
parent
dea8b6eef0
commit
dad31ec133
3 changed files with 434 additions and 0 deletions
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@ -13,8 +13,36 @@
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#ifndef __SOUND_MAX98095_PDATA_H__
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#define __SOUND_MAX98095_PDATA_H__
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/* Equalizer filter response configuration */
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struct max98095_eq_cfg {
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const char *name;
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unsigned int rate;
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u16 band1[5];
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u16 band2[5];
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u16 band3[5];
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u16 band4[5];
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u16 band5[5];
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};
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/* Biquad filter response configuration */
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struct max98095_biquad_cfg {
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const char *name;
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unsigned int rate;
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u16 band1[5];
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u16 band2[5];
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};
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/* codec platform data */
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struct max98095_pdata {
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/* Equalizers for DAI1 and DAI2 */
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struct max98095_eq_cfg *eq_cfg;
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unsigned int eq_cfgcnt;
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/* Biquad filter for DAI1 and DAI2 */
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struct max98095_biquad_cfg *bq_cfg;
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unsigned int bq_cfgcnt;
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/* Analog/digital microphone configuration:
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* 0 = analog microphone input (normal setting)
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* 1 = digital microphone input
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@ -34,6 +34,8 @@ enum max98095_type {
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struct max98095_cdata {
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unsigned int rate;
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unsigned int fmt;
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int eq_sel;
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int bq_sel;
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};
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struct max98095_priv {
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@ -42,6 +44,12 @@ struct max98095_priv {
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struct max98095_pdata *pdata;
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unsigned int sysclk;
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struct max98095_cdata dai[3];
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const char **eq_texts;
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const char **bq_texts;
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struct soc_enum eq_enum;
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struct soc_enum bq_enum;
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int eq_textcnt;
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int bq_textcnt;
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u8 lin_state;
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unsigned int mic1pre;
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unsigned int mic2pre;
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@ -602,6 +610,74 @@ static int max98095_volatile(struct snd_soc_codec *codec, unsigned int reg)
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return 0;
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}
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/*
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* Filter coefficients are in a separate register segment
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* and they share the address space of the normal registers.
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* The coefficient registers do not need or share the cache.
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*/
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static int max98095_hw_write(struct snd_soc_codec *codec, unsigned int reg,
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unsigned int value)
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{
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u8 data[2];
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data[0] = reg;
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data[1] = value;
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if (codec->hw_write(codec->control_data, data, 2) == 2)
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return 0;
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else
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return -EIO;
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}
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/*
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* Load equalizer DSP coefficient configurations registers
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*/
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static void m98095_eq_band(struct snd_soc_codec *codec, unsigned int dai,
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unsigned int band, u16 *coefs)
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{
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unsigned int eq_reg;
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unsigned int i;
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BUG_ON(band > 4);
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BUG_ON(dai > 1);
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/* Load the base register address */
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eq_reg = dai ? M98095_142_DAI2_EQ_BASE : M98095_110_DAI1_EQ_BASE;
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/* Add the band address offset, note adjustment for word address */
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eq_reg += band * (M98095_COEFS_PER_BAND << 1);
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/* Step through the registers and coefs */
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for (i = 0; i < M98095_COEFS_PER_BAND; i++) {
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max98095_hw_write(codec, eq_reg++, M98095_BYTE1(coefs[i]));
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max98095_hw_write(codec, eq_reg++, M98095_BYTE0(coefs[i]));
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}
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}
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/*
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* Load biquad filter coefficient configurations registers
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*/
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static void m98095_biquad_band(struct snd_soc_codec *codec, unsigned int dai,
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unsigned int band, u16 *coefs)
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{
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unsigned int bq_reg;
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unsigned int i;
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BUG_ON(band > 1);
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BUG_ON(dai > 1);
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/* Load the base register address */
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bq_reg = dai ? M98095_17E_DAI2_BQ_BASE : M98095_174_DAI1_BQ_BASE;
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/* Add the band address offset, note adjustment for word address */
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bq_reg += band * (M98095_COEFS_PER_BAND << 1);
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/* Step through the registers and coefs */
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for (i = 0; i < M98095_COEFS_PER_BAND; i++) {
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max98095_hw_write(codec, bq_reg++, M98095_BYTE1(coefs[i]));
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max98095_hw_write(codec, bq_reg++, M98095_BYTE0(coefs[i]));
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}
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}
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static const char * const max98095_fltr_mode[] = { "Voice", "Music" };
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static const struct soc_enum max98095_dai1_filter_mode_enum[] = {
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SOC_ENUM_SINGLE(M98095_02E_DAI1_FILTERS, 7, 2, max98095_fltr_mode),
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@ -792,6 +868,12 @@ static const struct snd_kcontrol_new max98095_snd_controls[] = {
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SOC_SINGLE_TLV("ADCR Boost Volume", M98095_05E_LVL_ADC_R, 4, 3, 0,
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max98095_adcboost_tlv),
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SOC_SINGLE("EQ1 Switch", M98095_088_CFG_LEVEL, 0, 1, 0),
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SOC_SINGLE("EQ2 Switch", M98095_088_CFG_LEVEL, 1, 1, 0),
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SOC_SINGLE("Biquad1 Switch", M98095_088_CFG_LEVEL, 2, 1, 0),
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SOC_SINGLE("Biquad2 Switch", M98095_088_CFG_LEVEL, 3, 1, 0),
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SOC_ENUM("DAI1 Filter Mode", max98095_dai1_filter_mode_enum),
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SOC_ENUM("DAI2 Filter Mode", max98095_dai2_filter_mode_enum),
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SOC_ENUM("DAI1 DAC Filter", max98095_dai1_dac_filter_enum),
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@ -1766,6 +1848,299 @@ static struct snd_soc_dai_driver max98095_dai[] = {
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};
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static int max98095_get_eq_channel(const char *name)
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{
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if (strcmp(name, "EQ1 Mode") == 0)
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return 0;
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if (strcmp(name, "EQ2 Mode") == 0)
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return 1;
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return -EINVAL;
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}
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static int max98095_put_eq_enum(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
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struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
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struct max98095_pdata *pdata = max98095->pdata;
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int channel = max98095_get_eq_channel(kcontrol->id.name);
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struct max98095_cdata *cdata;
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int sel = ucontrol->value.integer.value[0];
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struct max98095_eq_cfg *coef_set;
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int fs, best, best_val, i;
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int regmask, regsave;
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BUG_ON(channel > 1);
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cdata = &max98095->dai[channel];
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if (sel >= pdata->eq_cfgcnt)
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return -EINVAL;
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cdata->eq_sel = sel;
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if (!pdata || !max98095->eq_textcnt)
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return 0;
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fs = cdata->rate;
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/* Find the selected configuration with nearest sample rate */
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best = 0;
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best_val = INT_MAX;
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for (i = 0; i < pdata->eq_cfgcnt; i++) {
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if (strcmp(pdata->eq_cfg[i].name, max98095->eq_texts[sel]) == 0 &&
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abs(pdata->eq_cfg[i].rate - fs) < best_val) {
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best = i;
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best_val = abs(pdata->eq_cfg[i].rate - fs);
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}
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}
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dev_dbg(codec->dev, "Selected %s/%dHz for %dHz sample rate\n",
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pdata->eq_cfg[best].name,
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pdata->eq_cfg[best].rate, fs);
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coef_set = &pdata->eq_cfg[best];
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regmask = (channel == 0) ? M98095_EQ1EN : M98095_EQ2EN;
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/* Disable filter while configuring, and save current on/off state */
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regsave = snd_soc_read(codec, M98095_088_CFG_LEVEL);
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snd_soc_update_bits(codec, M98095_088_CFG_LEVEL, regmask, 0);
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mutex_lock(&codec->mutex);
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snd_soc_update_bits(codec, M98095_00F_HOST_CFG, M98095_SEG, M98095_SEG);
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m98095_eq_band(codec, channel, 0, coef_set->band1);
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m98095_eq_band(codec, channel, 1, coef_set->band2);
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m98095_eq_band(codec, channel, 2, coef_set->band3);
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m98095_eq_band(codec, channel, 3, coef_set->band4);
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m98095_eq_band(codec, channel, 4, coef_set->band5);
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snd_soc_update_bits(codec, M98095_00F_HOST_CFG, M98095_SEG, 0);
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mutex_unlock(&codec->mutex);
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/* Restore the original on/off state */
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snd_soc_update_bits(codec, M98095_088_CFG_LEVEL, regmask, regsave);
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return 0;
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}
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static int max98095_get_eq_enum(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
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struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
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int channel = max98095_get_eq_channel(kcontrol->id.name);
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struct max98095_cdata *cdata;
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cdata = &max98095->dai[channel];
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ucontrol->value.enumerated.item[0] = cdata->eq_sel;
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return 0;
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}
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static void max98095_handle_eq_pdata(struct snd_soc_codec *codec)
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{
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struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
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struct max98095_pdata *pdata = max98095->pdata;
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struct max98095_eq_cfg *cfg;
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unsigned int cfgcnt;
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int i, j;
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const char **t;
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int ret;
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struct snd_kcontrol_new controls[] = {
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SOC_ENUM_EXT("EQ1 Mode",
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max98095->eq_enum,
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max98095_get_eq_enum,
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max98095_put_eq_enum),
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SOC_ENUM_EXT("EQ2 Mode",
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max98095->eq_enum,
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max98095_get_eq_enum,
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max98095_put_eq_enum),
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};
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cfg = pdata->eq_cfg;
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cfgcnt = pdata->eq_cfgcnt;
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/* Setup an array of texts for the equalizer enum.
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* This is based on Mark Brown's equalizer driver code.
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*/
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max98095->eq_textcnt = 0;
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max98095->eq_texts = NULL;
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for (i = 0; i < cfgcnt; i++) {
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for (j = 0; j < max98095->eq_textcnt; j++) {
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if (strcmp(cfg[i].name, max98095->eq_texts[j]) == 0)
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break;
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}
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if (j != max98095->eq_textcnt)
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continue;
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/* Expand the array */
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t = krealloc(max98095->eq_texts,
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sizeof(char *) * (max98095->eq_textcnt + 1),
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GFP_KERNEL);
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if (t == NULL)
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continue;
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/* Store the new entry */
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t[max98095->eq_textcnt] = cfg[i].name;
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max98095->eq_textcnt++;
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max98095->eq_texts = t;
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}
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/* Now point the soc_enum to .texts array items */
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max98095->eq_enum.texts = max98095->eq_texts;
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max98095->eq_enum.max = max98095->eq_textcnt;
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ret = snd_soc_add_controls(codec, controls, ARRAY_SIZE(controls));
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if (ret != 0)
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dev_err(codec->dev, "Failed to add EQ control: %d\n", ret);
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}
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static int max98095_get_bq_channel(const char *name)
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{
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if (strcmp(name, "Biquad1 Mode") == 0)
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return 0;
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if (strcmp(name, "Biquad2 Mode") == 0)
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return 1;
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return -EINVAL;
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}
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static int max98095_put_bq_enum(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
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struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
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struct max98095_pdata *pdata = max98095->pdata;
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int channel = max98095_get_bq_channel(kcontrol->id.name);
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struct max98095_cdata *cdata;
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int sel = ucontrol->value.integer.value[0];
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struct max98095_biquad_cfg *coef_set;
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int fs, best, best_val, i;
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int regmask, regsave;
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BUG_ON(channel > 1);
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cdata = &max98095->dai[channel];
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if (sel >= pdata->bq_cfgcnt)
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return -EINVAL;
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cdata->bq_sel = sel;
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if (!pdata || !max98095->bq_textcnt)
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return 0;
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fs = cdata->rate;
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/* Find the selected configuration with nearest sample rate */
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best = 0;
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best_val = INT_MAX;
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for (i = 0; i < pdata->bq_cfgcnt; i++) {
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if (strcmp(pdata->bq_cfg[i].name, max98095->bq_texts[sel]) == 0 &&
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abs(pdata->bq_cfg[i].rate - fs) < best_val) {
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best = i;
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best_val = abs(pdata->bq_cfg[i].rate - fs);
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}
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}
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dev_dbg(codec->dev, "Selected %s/%dHz for %dHz sample rate\n",
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pdata->bq_cfg[best].name,
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pdata->bq_cfg[best].rate, fs);
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coef_set = &pdata->bq_cfg[best];
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regmask = (channel == 0) ? M98095_BQ1EN : M98095_BQ2EN;
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/* Disable filter while configuring, and save current on/off state */
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regsave = snd_soc_read(codec, M98095_088_CFG_LEVEL);
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snd_soc_update_bits(codec, M98095_088_CFG_LEVEL, regmask, 0);
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mutex_lock(&codec->mutex);
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snd_soc_update_bits(codec, M98095_00F_HOST_CFG, M98095_SEG, M98095_SEG);
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m98095_biquad_band(codec, channel, 0, coef_set->band1);
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m98095_biquad_band(codec, channel, 1, coef_set->band2);
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snd_soc_update_bits(codec, M98095_00F_HOST_CFG, M98095_SEG, 0);
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mutex_unlock(&codec->mutex);
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/* Restore the original on/off state */
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snd_soc_update_bits(codec, M98095_088_CFG_LEVEL, regmask, regsave);
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return 0;
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}
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static int max98095_get_bq_enum(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
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struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
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int channel = max98095_get_bq_channel(kcontrol->id.name);
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struct max98095_cdata *cdata;
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cdata = &max98095->dai[channel];
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ucontrol->value.enumerated.item[0] = cdata->bq_sel;
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return 0;
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}
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static void max98095_handle_bq_pdata(struct snd_soc_codec *codec)
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{
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struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
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struct max98095_pdata *pdata = max98095->pdata;
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struct max98095_biquad_cfg *cfg;
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unsigned int cfgcnt;
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int i, j;
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const char **t;
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int ret;
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struct snd_kcontrol_new controls[] = {
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SOC_ENUM_EXT("Biquad1 Mode",
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max98095->bq_enum,
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max98095_get_bq_enum,
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max98095_put_bq_enum),
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SOC_ENUM_EXT("Biquad2 Mode",
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max98095->bq_enum,
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max98095_get_bq_enum,
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max98095_put_bq_enum),
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};
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cfg = pdata->bq_cfg;
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cfgcnt = pdata->bq_cfgcnt;
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/* Setup an array of texts for the biquad enum.
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* This is based on Mark Brown's equalizer driver code.
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*/
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max98095->bq_textcnt = 0;
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max98095->bq_texts = NULL;
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for (i = 0; i < cfgcnt; i++) {
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for (j = 0; j < max98095->bq_textcnt; j++) {
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if (strcmp(cfg[i].name, max98095->bq_texts[j]) == 0)
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break;
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}
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if (j != max98095->bq_textcnt)
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continue;
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/* Expand the array */
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t = krealloc(max98095->bq_texts,
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sizeof(char *) * (max98095->bq_textcnt + 1),
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GFP_KERNEL);
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if (t == NULL)
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continue;
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/* Store the new entry */
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t[max98095->bq_textcnt] = cfg[i].name;
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max98095->bq_textcnt++;
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max98095->bq_texts = t;
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}
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||||
|
||||
/* Now point the soc_enum to .texts array items */
|
||||
max98095->bq_enum.texts = max98095->bq_texts;
|
||||
max98095->bq_enum.max = max98095->bq_textcnt;
|
||||
|
||||
ret = snd_soc_add_controls(codec, controls, ARRAY_SIZE(controls));
|
||||
if (ret != 0)
|
||||
dev_err(codec->dev, "Failed to add Biquad control: %d\n", ret);
|
||||
}
|
||||
|
||||
static void max98095_handle_pdata(struct snd_soc_codec *codec)
|
||||
{
|
||||
struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
|
||||
|
|
@ -1785,6 +2160,14 @@ static void max98095_handle_pdata(struct snd_soc_codec *codec)
|
|||
regval |= M98095_DIGMIC_R;
|
||||
|
||||
snd_soc_write(codec, M98095_087_CFG_MIC, regval);
|
||||
|
||||
/* Configure equalizers */
|
||||
if (pdata->eq_cfgcnt)
|
||||
max98095_handle_eq_pdata(codec);
|
||||
|
||||
/* Configure bi-quad filters */
|
||||
if (pdata->bq_cfgcnt)
|
||||
max98095_handle_bq_pdata(codec);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
|
|
@ -1855,18 +2238,26 @@ static int max98095_probe(struct snd_soc_codec *codec)
|
|||
/* initialize private data */
|
||||
|
||||
max98095->sysclk = (unsigned)-1;
|
||||
max98095->eq_textcnt = 0;
|
||||
max98095->bq_textcnt = 0;
|
||||
|
||||
cdata = &max98095->dai[0];
|
||||
cdata->rate = (unsigned)-1;
|
||||
cdata->fmt = (unsigned)-1;
|
||||
cdata->eq_sel = 0;
|
||||
cdata->bq_sel = 0;
|
||||
|
||||
cdata = &max98095->dai[1];
|
||||
cdata->rate = (unsigned)-1;
|
||||
cdata->fmt = (unsigned)-1;
|
||||
cdata->eq_sel = 0;
|
||||
cdata->bq_sel = 0;
|
||||
|
||||
cdata = &max98095->dai[2];
|
||||
cdata->rate = (unsigned)-1;
|
||||
cdata->fmt = (unsigned)-1;
|
||||
cdata->eq_sel = 0;
|
||||
cdata->bq_sel = 0;
|
||||
|
||||
max98095->lin_state = 0;
|
||||
max98095->mic1pre = 0;
|
||||
|
|
|
|||
|
|
@ -250,6 +250,8 @@
|
|||
/* M98095_088_CFG_LEVEL */
|
||||
#define M98095_VSEN (1<<6)
|
||||
#define M98095_ZDEN (1<<5)
|
||||
#define M98095_BQ2EN (1<<3)
|
||||
#define M98095_BQ1EN (1<<2)
|
||||
#define M98095_EQ2EN (1<<1)
|
||||
#define M98095_EQ1EN (1<<0)
|
||||
|
||||
|
|
@ -281,4 +283,17 @@
|
|||
#define M98095_PWRSV8K (1<<1)
|
||||
#define M98095_PWRSV (1<<0)
|
||||
|
||||
#define M98095_COEFS_PER_BAND 5
|
||||
|
||||
#define M98095_BYTE1(w) ((w >> 8) & 0xff)
|
||||
#define M98095_BYTE0(w) (w & 0xff)
|
||||
|
||||
/* Equalizer filter coefficients */
|
||||
#define M98095_110_DAI1_EQ_BASE 0x10
|
||||
#define M98095_142_DAI2_EQ_BASE 0x42
|
||||
|
||||
/* Biquad filter coefficients */
|
||||
#define M98095_174_DAI1_BQ_BASE 0x74
|
||||
#define M98095_17E_DAI2_BQ_BASE 0x7E
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in a new issue