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ARM: SoC fixes

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A bigger batch than I anticipated this week, for two reasons:
 
  - Some fallout on Davinci from board file -> DTB conversion, that also
  includes a few longer-standing fixes (i.e. not recent regressions).
 
  - drivers/reset material that has been in linux-next for a while, but
  didn't get sent to us until now for a variety of reasons (maintainer out
  sick, holidays, etc). There's a functional dependency in there such that
  one platform (Altera's SoCFPGA) won't boot without one of the patches;
  instead of reverting the patch that got merged, I looked at this set
  and decided it was small enough that I'll pick it up anyway. If you
  disagree I can revisit with a smaller set.
 
 That being said, there's also a handful of the usual stuff:
 
  - Fix for a crash on Armada 7K/8K when the kernel touches PSCI-reserved
  memory
  - Fix for PCIe reset on Macchiatobin (Armada 8K development board, what
  this email is sent from in fact :)
  - Enable a few new-merged modules for Amlogic in arm64 defconfig
  - Error path fixes on Integrator
  - Build fix for Renesas and Qualcomm
  - Initialization fix for Renesas RZ/G2E
 
  + A few more fixlets.
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Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC fixes from Olof Johansson:
 "A bigger batch than I anticipated this week, for two reasons:

   - Some fallout on Davinci from board file -> DTB conversion, that
     also includes a few longer-standing fixes (i.e. not recent
     regressions).

   - drivers/reset material that has been in linux-next for a while, but
     didn't get sent to us until now for a variety of reasons
     (maintainer out sick, holidays, etc). There's a functional
     dependency in there such that one platform (Altera's SoCFPGA) won't
     boot without one of the patches; instead of reverting the patch
     that got merged, I looked at this set and decided it was small
     enough that I'll pick it up anyway. If you disagree I can revisit
     with a smaller set.

  That being said, there's also a handful of the usual stuff:

   - Fix for a crash on Armada 7K/8K when the kernel touches
     PSCI-reserved memory

   - Fix for PCIe reset on Macchiatobin (Armada 8K development board,
     what this email is sent from in fact :)

   - Enable a few new-merged modules for Amlogic in arm64 defconfig

   - Error path fixes on Integrator

   - Build fix for Renesas and Qualcomm

   - Initialization fix for Renesas RZ/G2E

  .. plus a few more fixlets"

* tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (28 commits)
  ARM: integrator: impd1: use struct_size() in devm_kzalloc()
  qcom-scm: Include <linux/err.h> header
  gpio: pl061: handle failed allocations
  ARM: dts: kirkwood: Fix polarity of GPIO fan lines
  arm64: dts: marvell: mcbin: fix PCIe reset signal
  arm64: dts: marvell: armada-ap806: reserve PSCI area
  ARM: dts: da850-lcdk: Correct the sound card name
  ARM: dts: da850-lcdk: Correct the audio codec regulators
  ARM: dts: da850-evm: Correct the sound card name
  ARM: dts: da850-evm: Correct the audio codec regulators
  ARM: davinci: omapl138-hawk: fix label names in GPIO lookup entries
  ARM: davinci: dm644x-evm: fix label names in GPIO lookup entries
  ARM: davinci: dm355-evm: fix label names in GPIO lookup entries
  ARM: davinci: da850-evm: fix label names in GPIO lookup entries
  ARM: davinci: da830-evm: fix label names in GPIO lookup entries
  arm64: defconfig: enable modules for amlogic s400 sound card
  reset: uniphier-glue: Add AHCI reset control support in glue layer
  dt-bindings: reset: uniphier: Add AHCI core reset description
  reset: uniphier-usb3: Rename to reset-uniphier-glue
  dt-bindings: reset: uniphier: Replace the expression of USB3 with generic peripherals
  ...
This commit is contained in:
Linus Torvalds 2019-01-14 10:34:14 +12:00
commit dbc3c09b81
26 changed files with 321 additions and 93 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

3
Documentation/devicetree/bindings/reset/socfpga-reset.txt
View file

@ -1,7 +1,8 @@
Altera SOCFPGA Reset Manager
Required properties:
- compatible : "altr,rst-mgr"
- compatible : "altr,rst-mgr" for (Cyclone5/Arria5/Arria10)
"altr,stratix10-rst-mgr","altr,rst-mgr" for Stratix10 ARM64 SoC
- reg : Should contain 1 register ranges(address and length)
- altr,modrst-offset : Should contain the offset of the first modrst register.
- #reset-cells: 1

25
Documentation/devicetree/bindings/reset/uniphier-reset.txt
View file

@ -120,27 +120,30 @@ Example:
};
USB3 core reset
---------------
Peripheral core reset in glue layer
-----------------------------------
USB3 core reset belongs to USB3 glue layer. Before using the core reset,
it is necessary to control the clocks and resets to enable this layer.
These clocks and resets should be described in each property.
Some peripheral core reset belongs to its own glue layer. Before using
this core reset, it is necessary to control the clocks and resets to enable
this layer. These clocks and resets should be described in each property.
Required properties:
- compatible: Should be
"socionext,uniphier-pro4-usb3-reset" - for Pro4 SoC
"socionext,uniphier-pxs2-usb3-reset" - for PXs2 SoC
"socionext,uniphier-ld20-usb3-reset" - for LD20 SoC
"socionext,uniphier-pxs3-usb3-reset" - for PXs3 SoC
"socionext,uniphier-pro4-usb3-reset" - for Pro4 SoC USB3
"socionext,uniphier-pxs2-usb3-reset" - for PXs2 SoC USB3
"socionext,uniphier-ld20-usb3-reset" - for LD20 SoC USB3
"socionext,uniphier-pxs3-usb3-reset" - for PXs3 SoC USB3
"socionext,uniphier-pro4-ahci-reset" - for Pro4 SoC AHCI
"socionext,uniphier-pxs2-ahci-reset" - for PXs2 SoC AHCI
"socionext,uniphier-pxs3-ahci-reset" - for PXs3 SoC AHCI
- #reset-cells: Should be 1.
- reg: Specifies offset and length of the register set for the device.
- clocks: A list of phandles to the clock gate for USB3 glue layer.
- clocks: A list of phandles to the clock gate for the glue layer.
According to the clock-names, appropriate clocks are required.
- clock-names: Should contain
"gio", "link" - for Pro4 SoC
"link" - for others
- resets: A list of phandles to the reset control for USB3 glue layer.
- resets: A list of phandles to the reset control for the glue layer.
According to the reset-names, appropriate resets are required.
- reset-names: Should contain
"gio", "link" - for Pro4 SoC

31
arch/arm/boot/dts/da850-evm.dts
View file

@ -94,6 +94,28 @@
regulator-boot-on;
};
baseboard_3v3: fixedregulator-3v3 {
/* TPS73701DCQ */
compatible = "regulator-fixed";
regulator-name = "baseboard_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vbat>;
regulator-always-on;
regulator-boot-on;
};
baseboard_1v8: fixedregulator-1v8 {
/* TPS73701DCQ */
compatible = "regulator-fixed";
regulator-name = "baseboard_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vbat>;
regulator-always-on;
regulator-boot-on;
};
backlight_lcd: backlight-regulator {
compatible = "regulator-fixed";
regulator-name = "lcd_backlight_pwr";
@ -105,7 +127,7 @@
sound {
compatible = "simple-audio-card";
simple-audio-card,name = "DA850/OMAP-L138 EVM";
simple-audio-card,name = "DA850-OMAPL138 EVM";
simple-audio-card,widgets =
"Line", "Line In",
"Line", "Line Out";
@ -210,10 +232,9 @@
/* Regulators */
IOVDD-supply = <&vdcdc2_reg>;
/* Derived from VBAT: Baseboard 3.3V / 1.8V */
AVDD-supply = <&vbat>;
DRVDD-supply = <&vbat>;
DVDD-supply = <&vbat>;
AVDD-supply = <&baseboard_3v3>;
DRVDD-supply = <&baseboard_3v3>;
DVDD-supply = <&baseboard_1v8>;
};
tca6416: gpio@20 {
compatible = "ti,tca6416";

38
arch/arm/boot/dts/da850-lcdk.dts
View file

@ -39,9 +39,39 @@
};
};
vcc_5vd: fixedregulator-vcc_5vd {
compatible = "regulator-fixed";
regulator-name = "vcc_5vd";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-boot-on;
};
vcc_3v3d: fixedregulator-vcc_3v3d {
/* TPS650250 - VDCDC1 */
compatible = "regulator-fixed";
regulator-name = "vcc_3v3d";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc_5vd>;
regulator-always-on;
regulator-boot-on;
};
vcc_1v8d: fixedregulator-vcc_1v8d {
/* TPS650250 - VDCDC2 */
compatible = "regulator-fixed";
regulator-name = "vcc_1v8d";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vcc_5vd>;
regulator-always-on;
regulator-boot-on;
};
sound {
compatible = "simple-audio-card";
simple-audio-card,name = "DA850/OMAP-L138 LCDK";
simple-audio-card,name = "DA850-OMAPL138 LCDK";
simple-audio-card,widgets =
"Line", "Line In",
"Line", "Line Out";
@ -221,6 +251,12 @@
compatible = "ti,tlv320aic3106";
reg = <0x18>;
status = "okay";
/* Regulators */
IOVDD-supply = <&vcc_3v3d>;
AVDD-supply = <&vcc_3v3d>;
DRVDD-supply = <&vcc_3v3d>;
DVDD-supply = <&vcc_1v8d>;
};
};

4
arch/arm/boot/dts/kirkwood-dnskw.dtsi
View file

@ -36,8 +36,8 @@
compatible = "gpio-fan";
pinctrl-0 = <&pmx_fan_high_speed &pmx_fan_low_speed>;
pinctrl-names = "default";
gpios = <&gpio1 14 GPIO_ACTIVE_LOW
&gpio1 13 GPIO_ACTIVE_LOW>;
gpios = <&gpio1 14 GPIO_ACTIVE_HIGH
&gpio1 13 GPIO_ACTIVE_HIGH>;
gpio-fan,speed-map = <0 0
3000 1
6000 2>;

4
arch/arm/mach-davinci/board-da830-evm.c
View file

@ -208,9 +208,9 @@ static struct gpiod_lookup_table mmc_gpios_table = {
.dev_id = "da830-mmc.0",
.table = {
/* gpio chip 1 contains gpio range 32-63 */
GPIO_LOOKUP("davinci_gpio.0", DA830_MMCSD_CD_PIN, "cd",
GPIO_LOOKUP("davinci_gpio", DA830_MMCSD_CD_PIN, "cd",
GPIO_ACTIVE_LOW),
GPIO_LOOKUP("davinci_gpio.0", DA830_MMCSD_WP_PIN, "wp",
GPIO_LOOKUP("davinci_gpio", DA830_MMCSD_WP_PIN, "wp",
GPIO_ACTIVE_LOW),
},
};

4
arch/arm/mach-davinci/board-da850-evm.c
View file

@ -805,9 +805,9 @@ static struct gpiod_lookup_table mmc_gpios_table = {
.dev_id = "da830-mmc.0",
.table = {
/* gpio chip 2 contains gpio range 64-95 */
GPIO_LOOKUP("davinci_gpio.0", DA850_MMCSD_CD_PIN, "cd",
GPIO_LOOKUP("davinci_gpio", DA850_MMCSD_CD_PIN, "cd",
GPIO_ACTIVE_LOW),
GPIO_LOOKUP("davinci_gpio.0", DA850_MMCSD_WP_PIN, "wp",
GPIO_LOOKUP("davinci_gpio", DA850_MMCSD_WP_PIN, "wp",
GPIO_ACTIVE_HIGH),
},
};

4
arch/arm/mach-davinci/board-dm355-evm.c
View file

@ -117,9 +117,9 @@ static struct platform_device davinci_nand_device = {
static struct gpiod_lookup_table i2c_recovery_gpiod_table = {
.dev_id = "i2c_davinci.1",
.table = {
GPIO_LOOKUP("davinci_gpio.0", DM355_I2C_SDA_PIN, "sda",
GPIO_LOOKUP("davinci_gpio", DM355_I2C_SDA_PIN, "sda",
GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
GPIO_LOOKUP("davinci_gpio.0", DM355_I2C_SCL_PIN, "scl",
GPIO_LOOKUP("davinci_gpio", DM355_I2C_SCL_PIN, "scl",
GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
},
};

4
arch/arm/mach-davinci/board-dm644x-evm.c
View file

@ -660,9 +660,9 @@ static struct i2c_board_info __initdata i2c_info[] = {
static struct gpiod_lookup_table i2c_recovery_gpiod_table = {
.dev_id = "i2c_davinci.1",
.table = {
GPIO_LOOKUP("davinci_gpio.0", DM644X_I2C_SDA_PIN, "sda",
GPIO_LOOKUP("davinci_gpio", DM644X_I2C_SDA_PIN, "sda",
GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
GPIO_LOOKUP("davinci_gpio.0", DM644X_I2C_SCL_PIN, "scl",
GPIO_LOOKUP("davinci_gpio", DM644X_I2C_SCL_PIN, "scl",
GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
},
};

4
arch/arm/mach-davinci/board-omapl138-hawk.c
View file

@ -134,9 +134,9 @@ static const short hawk_mmcsd0_pins[] = {
static struct gpiod_lookup_table mmc_gpios_table = {
.dev_id = "da830-mmc.0",
.table = {
GPIO_LOOKUP("davinci_gpio.0", DA850_HAWK_MMCSD_CD_PIN, "cd",
GPIO_LOOKUP("davinci_gpio", DA850_HAWK_MMCSD_CD_PIN, "cd",
GPIO_ACTIVE_LOW),
GPIO_LOOKUP("davinci_gpio.0", DA850_HAWK_MMCSD_WP_PIN, "wp",
GPIO_LOOKUP("davinci_gpio", DA850_HAWK_MMCSD_WP_PIN, "wp",
GPIO_ACTIVE_LOW),
},
};

8
arch/arm/mach-integrator/impd1.c
View file

@ -390,10 +390,14 @@ static int __ref impd1_probe(struct lm_device *dev)
char *mmciname;
lookup = devm_kzalloc(&dev->dev,
sizeof(*lookup) + 3 * sizeof(struct gpiod_lookup),
struct_size(lookup, table, 3),
GFP_KERNEL);
chipname = devm_kstrdup(&dev->dev, devname, GFP_KERNEL);
mmciname = kasprintf(GFP_KERNEL, "lm%x:00700", dev->id);
mmciname = devm_kasprintf(&dev->dev, GFP_KERNEL,
"lm%x:00700", dev->id);
if (!lookup || !chipname || !mmciname)
return -ENOMEM;
lookup->dev_id = mmciname;
/*
* Offsets on GPIO block 1:

4
arch/arm/mach-socfpga/socfpga.c
View file

@ -32,6 +32,8 @@ void __iomem *rst_manager_base_addr;
void __iomem *sdr_ctl_base_addr;
unsigned long socfpga_cpu1start_addr;
extern void __init socfpga_reset_init(void);
static void __init socfpga_sysmgr_init(void)
{
struct device_node *np;
@ -64,6 +66,7 @@ static void __init socfpga_init_irq(void)
if (IS_ENABLED(CONFIG_EDAC_ALTERA_OCRAM))
socfpga_init_ocram_ecc();
socfpga_reset_init();
}
static void __init socfpga_arria10_init_irq(void)
@ -74,6 +77,7 @@ static void __init socfpga_arria10_init_irq(void)
socfpga_init_arria10_l2_ecc();
if (IS_ENABLED(CONFIG_EDAC_ALTERA_OCRAM))
socfpga_init_arria10_ocram_ecc();
socfpga_reset_init();
}
static void socfpga_cyclone5_restart(enum reboot_mode mode, const char *cmd)

2
arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
View file

@ -183,7 +183,7 @@
pinctrl-0 = <&cp0_pcie_pins>;
num-lanes = <4>;
num-viewport = <8>;
reset-gpio = <&cp0_gpio1 20 GPIO_ACTIVE_LOW>;
reset-gpios = <&cp0_gpio2 20 GPIO_ACTIVE_LOW>;
status = "okay";
};

17
arch/arm64/boot/dts/marvell/armada-ap806.dtsi
View file

@ -28,6 +28,23 @@
method = "smc";
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
/*
* This area matches the mapping done with a
* mainline U-Boot, and should be updated by the
* bootloader.
*/
psci-area@4000000 {
reg = <0x0 0x4000000 0x0 0x200000>;
no-map;
};
};
ap806 {
#address-cells = <2>;
#size-cells = <2>;

4
arch/arm64/configs/defconfig
View file

@ -506,11 +506,15 @@ CONFIG_SND_SOC_ROCKCHIP=m
CONFIG_SND_SOC_ROCKCHIP_SPDIF=m
CONFIG_SND_SOC_ROCKCHIP_RT5645=m
CONFIG_SND_SOC_RK3399_GRU_SOUND=m
CONFIG_SND_MESON_AXG_SOUND_CARD=m
CONFIG_SND_SOC_SAMSUNG=y
CONFIG_SND_SOC_RCAR=m
CONFIG_SND_SOC_AK4613=m
CONFIG_SND_SIMPLE_CARD=m
CONFIG_SND_AUDIO_GRAPH_CARD=m
CONFIG_SND_SOC_ES7134=m
CONFIG_SND_SOC_ES7241=m
CONFIG_SND_SOC_TAS571X=m
CONFIG_I2C_HID=m
CONFIG_USB=y
CONFIG_USB_OTG=y

20
drivers/reset/Kconfig
View file

@ -109,7 +109,7 @@ config RESET_QCOM_PDC
config RESET_SIMPLE
bool "Simple Reset Controller Driver" if COMPILE_TEST
default ARCH_SOCFPGA || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARCH_ASPEED
default ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARCH_ASPEED
help
This enables a simple reset controller driver for reset lines that
that can be asserted and deasserted by toggling bits in a contiguous,
@ -128,6 +128,14 @@ config RESET_STM32MP157
help
This enables the RCC reset controller driver for STM32 MPUs.
config RESET_SOCFPGA
bool "SoCFPGA Reset Driver" if COMPILE_TEST && !ARCH_SOCFPGA
default ARCH_SOCFPGA
select RESET_SIMPLE
help
This enables the reset driver for the SoCFPGA ARMv7 platforms. This
driver gets initialized early during platform init calls.
config RESET_SUNXI
bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI
default ARCH_SUNXI
@ -163,15 +171,15 @@ config RESET_UNIPHIER
Say Y if you want to control reset signals provided by System Control
block, Media I/O block, Peripheral Block.
config RESET_UNIPHIER_USB3
tristate "USB3 reset driver for UniPhier SoCs"
config RESET_UNIPHIER_GLUE
tristate "Reset driver in glue layer for UniPhier SoCs"
depends on (ARCH_UNIPHIER || COMPILE_TEST) && OF
default ARCH_UNIPHIER
select RESET_SIMPLE
help
Support for the USB3 core reset on UniPhier SoCs.
Say Y if you want to control reset signals provided by
USB3 glue layer.
Support for peripheral core reset included in its own glue layer
on UniPhier SoCs. Say Y if you want to control reset signals
provided by the glue layer.
config RESET_ZYNQ
bool "ZYNQ Reset Driver" if COMPILE_TEST

3
drivers/reset/Makefile
View file

@ -19,10 +19,11 @@ obj-$(CONFIG_RESET_QCOM_AOSS) += reset-qcom-aoss.o
obj-$(CONFIG_RESET_QCOM_PDC) += reset-qcom-pdc.o
obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
obj-$(CONFIG_RESET_STM32MP157) += reset-stm32mp1.o
obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o
obj-$(CONFIG_RESET_TI_SYSCON) += reset-ti-syscon.o
obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
obj-$(CONFIG_RESET_UNIPHIER_USB3) += reset-uniphier-usb3.o
obj-$(CONFIG_RESET_UNIPHIER_GLUE) += reset-uniphier-glue.o
obj-$(CONFIG_RESET_ZYNQ) += reset-zynq.o

42
drivers/reset/core.c
View file

@ -795,3 +795,45 @@ devm_reset_control_array_get(struct device *dev, bool shared, bool optional)
return rstc;
}
EXPORT_SYMBOL_GPL(devm_reset_control_array_get);
static int reset_control_get_count_from_lookup(struct device *dev)
{
const struct reset_control_lookup *lookup;
const char *dev_id;
int count = 0;
if (!dev)
return -EINVAL;
dev_id = dev_name(dev);
mutex_lock(&reset_lookup_mutex);
list_for_each_entry(lookup, &reset_lookup_list, list) {
if (!strcmp(lookup->dev_id, dev_id))
count++;
}
mutex_unlock(&reset_lookup_mutex);
if (count == 0)
count = -ENOENT;
return count;
}
/**
* reset_control_get_count - Count number of resets available with a device
*
* @dev: device for which to return the number of resets
*
* Returns positive reset count on success, or error number on failure and
* on count being zero.
*/
int reset_control_get_count(struct device *dev)
{
if (dev->of_node)
return of_reset_control_get_count(dev->of_node);
return reset_control_get_count_from_lookup(dev);
}
EXPORT_SYMBOL_GPL(reset_control_get_count);

1
drivers/reset/reset-hsdk.c
View file

@ -86,6 +86,7 @@ static int hsdk_reset_reset(struct reset_controller_dev *rcdev,
static const struct reset_control_ops hsdk_reset_ops = {
.reset = hsdk_reset_reset,
.deassert = hsdk_reset_reset,
};
static int hsdk_reset_probe(struct platform_device *pdev)

13
drivers/reset/reset-simple.c
View file

@ -109,7 +109,7 @@ struct reset_simple_devdata {
#define SOCFPGA_NR_BANKS 8
static const struct reset_simple_devdata reset_simple_socfpga = {
.reg_offset = 0x10,
.reg_offset = 0x20,
.nr_resets = SOCFPGA_NR_BANKS * 32,
.status_active_low = true,
};
@ -120,7 +120,8 @@ static const struct reset_simple_devdata reset_simple_active_low = {
};
static const struct of_device_id reset_simple_dt_ids[] = {
{ .compatible = "altr,rst-mgr", .data = &reset_simple_socfpga },
{ .compatible = "altr,stratix10-rst-mgr",
.data = &reset_simple_socfpga },
{ .compatible = "st,stm32-rcc", },
{ .compatible = "allwinner,sun6i-a31-clock-reset",
.data = &reset_simple_active_low },
@ -166,14 +167,6 @@ static int reset_simple_probe(struct platform_device *pdev)
data->status_active_low = devdata->status_active_low;
}
if (of_device_is_compatible(dev->of_node, "altr,rst-mgr") &&
of_property_read_u32(dev->of_node, "altr,modrst-offset",
&reg_offset)) {
dev_warn(dev,
"missing altr,modrst-offset property, assuming 0x%x!\n",
reg_offset);
}
data->membase += reg_offset;
return devm_reset_controller_register(dev, &data->rcdev);

88
drivers/reset/reset-socfpga.c Normal file
View file

@ -0,0 +1,88 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2018, Intel Corporation
* Copied from reset-sunxi.c
*/
#include <linux/err.h>
#include <linux/io.h>
#include <linux/init.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/reset-controller.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/types.h>
#include "reset-simple.h"
#define SOCFPGA_NR_BANKS 8
void __init socfpga_reset_init(void);
static int a10_reset_init(struct device_node *np)
{
struct reset_simple_data *data;
struct resource res;
resource_size_t size;
int ret;
u32 reg_offset = 0x10;
data = kzalloc(sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
ret = of_address_to_resource(np, 0, &res);
if (ret)
goto err_alloc;
size = resource_size(&res);
if (!request_mem_region(res.start, size, np->name)) {
ret = -EBUSY;
goto err_alloc;
}
data->membase = ioremap(res.start, size);
if (!data->membase) {
ret = -ENOMEM;
goto err_alloc;
}
if (of_property_read_u32(np, "altr,modrst-offset", &reg_offset))
pr_warn("missing altr,modrst-offset property, assuming 0x10\n");
data->membase += reg_offset;
spin_lock_init(&data->lock);
data->rcdev.owner = THIS_MODULE;
data->rcdev.nr_resets = SOCFPGA_NR_BANKS * 32;
data->rcdev.ops = &reset_simple_ops;
data->rcdev.of_node = np;
data->status_active_low = true;
return reset_controller_register(&data->rcdev);
err_alloc:
kfree(data);
return ret;
};
/*
* These are the reset controller we need to initialize early on in
* our system, before we can even think of using a regular device
* driver for it.
* The controllers that we can register through the regular device
* model are handled by the simple reset driver directly.
*/
static const struct of_device_id socfpga_early_reset_dt_ids[] __initconst = {
{ .compatible = "altr,rst-mgr", },
{ /* sentinel */ },
};
void __init socfpga_reset_init(void)
{
struct device_node *np;
for_each_matching_node(np, socfpga_early_reset_dt_ids)
a10_reset_init(np);
}

50
drivers/reset/reset-uniphier-usb3.c → drivers/reset/reset-uniphier-glue.c
View file

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
//
// reset-uniphier-usb3.c - USB3 reset driver for UniPhier
// reset-uniphier-glue.c - Glue layer reset driver for UniPhier
// Copyright 2018 Socionext Inc.
// Author: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
@ -15,24 +15,24 @@
#define MAX_CLKS 2
#define MAX_RSTS 2
struct uniphier_usb3_reset_soc_data {
struct uniphier_glue_reset_soc_data {
int nclks;
const char * const *clock_names;
int nrsts;
const char * const *reset_names;
};
struct uniphier_usb3_reset_priv {
struct uniphier_glue_reset_priv {
struct clk_bulk_data clk[MAX_CLKS];
struct reset_control *rst[MAX_RSTS];
struct reset_simple_data rdata;
const struct uniphier_usb3_reset_soc_data *data;
const struct uniphier_glue_reset_soc_data *data;
};
static int uniphier_usb3_reset_probe(struct platform_device *pdev)
static int uniphier_glue_reset_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct uniphier_usb3_reset_priv *priv;
struct uniphier_glue_reset_priv *priv;
struct resource *res;
resource_size_t size;
const char *name;
@ -100,9 +100,9 @@ out_rst_assert:
return ret;
}
static int uniphier_usb3_reset_remove(struct platform_device *pdev)
static int uniphier_glue_reset_remove(struct platform_device *pdev)
{
struct uniphier_usb3_reset_priv *priv = platform_get_drvdata(pdev);
struct uniphier_glue_reset_priv *priv = platform_get_drvdata(pdev);
int i;
for (i = 0; i < priv->data->nrsts; i++)
@ -117,7 +117,7 @@ static const char * const uniphier_pro4_clock_reset_names[] = {
"gio", "link",
};
static const struct uniphier_usb3_reset_soc_data uniphier_pro4_data = {
static const struct uniphier_glue_reset_soc_data uniphier_pro4_data = {
.nclks = ARRAY_SIZE(uniphier_pro4_clock_reset_names),
.clock_names = uniphier_pro4_clock_reset_names,
.nrsts = ARRAY_SIZE(uniphier_pro4_clock_reset_names),
@ -128,14 +128,14 @@ static const char * const uniphier_pxs2_clock_reset_names[] = {
"link",
};
static const struct uniphier_usb3_reset_soc_data uniphier_pxs2_data = {
static const struct uniphier_glue_reset_soc_data uniphier_pxs2_data = {
.nclks = ARRAY_SIZE(uniphier_pxs2_clock_reset_names),
.clock_names = uniphier_pxs2_clock_reset_names,
.nrsts = ARRAY_SIZE(uniphier_pxs2_clock_reset_names),
.reset_names = uniphier_pxs2_clock_reset_names,
};
static const struct of_device_id uniphier_usb3_reset_match[] = {
static const struct of_device_id uniphier_glue_reset_match[] = {
{
.compatible = "socionext,uniphier-pro4-usb3-reset",
.data = &uniphier_pro4_data,
@ -152,20 +152,32 @@ static const struct of_device_id uniphier_usb3_reset_match[] = {
.compatible = "socionext,uniphier-pxs3-usb3-reset",
.data = &uniphier_pxs2_data,
},
{
.compatible = "socionext,uniphier-pro4-ahci-reset",
.data = &uniphier_pro4_data,
},
{
.compatible = "socionext,uniphier-pxs2-ahci-reset",
.data = &uniphier_pxs2_data,
},
{
.compatible = "socionext,uniphier-pxs3-ahci-reset",
.data = &uniphier_pxs2_data,
},
{ /* Sentinel */ }
};
MODULE_DEVICE_TABLE(of, uniphier_usb3_reset_match);
MODULE_DEVICE_TABLE(of, uniphier_glue_reset_match);
static struct platform_driver uniphier_usb3_reset_driver = {
.probe = uniphier_usb3_reset_probe,
.remove = uniphier_usb3_reset_remove,
static struct platform_driver uniphier_glue_reset_driver = {
.probe = uniphier_glue_reset_probe,
.remove = uniphier_glue_reset_remove,
.driver = {
.name = "uniphier-usb3-reset",
.of_match_table = uniphier_usb3_reset_match,
.name = "uniphier-glue-reset",
.of_match_table = uniphier_glue_reset_match,
},
};
module_platform_driver(uniphier_usb3_reset_driver);
module_platform_driver(uniphier_glue_reset_driver);
MODULE_AUTHOR("Kunihiko Hayashi <hayashi.kunihiko@socionext.com>");
MODULE_DESCRIPTION("UniPhier USB3 Reset Driver");
MODULE_DESCRIPTION("UniPhier Glue layer reset driver");
MODULE_LICENSE("GPL");

2
drivers/soc/renesas/Kconfig
View file

@ -44,7 +44,7 @@ config ARCH_RZN1
bool
select ARM_AMBA
if ARM
if ARM && ARCH_RENESAS
#comment "Renesas ARM SoCs System Type"

23
drivers/soc/renesas/r8a774c0-sysc.c
View file

@ -28,19 +28,6 @@ static struct rcar_sysc_area r8a774c0_areas[] __initdata = {
{ "3dg-b", 0x100, 1, R8A774C0_PD_3DG_B, R8A774C0_PD_3DG_A },
};
static void __init rcar_sysc_fix_parent(struct rcar_sysc_area *areas,
unsigned int num_areas, u8 id,
int new_parent)
{
unsigned int i;
for (i = 0; i < num_areas; i++)
if (areas[i].isr_bit == id) {
areas[i].parent = new_parent;
return;
}
}
/* Fixups for RZ/G2E ES1.0 revision */
static const struct soc_device_attribute r8a774c0[] __initconst = {
{ .soc_id = "r8a774c0", .revision = "ES1.0" },
@ -50,12 +37,10 @@ static const struct soc_device_attribute r8a774c0[] __initconst = {
static int __init r8a774c0_sysc_init(void)
{
if (soc_device_match(r8a774c0)) {
rcar_sysc_fix_parent(r8a774c0_areas,
ARRAY_SIZE(r8a774c0_areas),
R8A774C0_PD_3DG_A, R8A774C0_PD_3DG_B);
rcar_sysc_fix_parent(r8a774c0_areas,
ARRAY_SIZE(r8a774c0_areas),
R8A774C0_PD_3DG_B, R8A774C0_PD_ALWAYS_ON);
/* Fix incorrect 3DG hierarchy */
swap(r8a774c0_areas[6], r8a774c0_areas[7]);
r8a774c0_areas[6].parent = R8A774C0_PD_ALWAYS_ON;
r8a774c0_areas[7].parent = R8A774C0_PD_3DG_B;
}
return 0;

1
include/linux/qcom_scm.h
View file

@ -13,6 +13,7 @@
#ifndef __QCOM_SCM_H
#define __QCOM_SCM_H
#include <linux/err.h>
#include <linux/types.h>
#include <linux/cpumask.h>

15
include/linux/reset.h
View file

@ -32,6 +32,8 @@ struct reset_control *devm_reset_control_array_get(struct device *dev,
struct reset_control *of_reset_control_array_get(struct device_node *np,
bool shared, bool optional);
int reset_control_get_count(struct device *dev);
#else
static inline int reset_control_reset(struct reset_control *rstc)
@ -97,6 +99,11 @@ of_reset_control_array_get(struct device_node *np, bool shared, bool optional)
return optional ? NULL : ERR_PTR(-ENOTSUPP);
}
static inline int reset_control_get_count(struct device *dev)
{
return -ENOENT;
}
#endif /* CONFIG_RESET_CONTROLLER */
static inline int __must_check device_reset(struct device *dev)
@ -138,7 +145,7 @@ __must_check reset_control_get_exclusive(struct device *dev, const char *id)
*
* Returns a struct reset_control or IS_ERR() condition containing errno.
* This function is intended for use with reset-controls which are shared
* between hardware-blocks.
* between hardware blocks.
*
* When a reset-control is shared, the behavior of reset_control_assert /
* deassert is changed, the reset-core will keep track of a deassert_count
@ -187,7 +194,7 @@ static inline struct reset_control *of_reset_control_get_exclusive(
}
/**
* of_reset_control_get_shared - Lookup and obtain an shared reference
* of_reset_control_get_shared - Lookup and obtain a shared reference
* to a reset controller.
* @node: device to be reset by the controller
* @id: reset line name
@ -229,7 +236,7 @@ static inline struct reset_control *of_reset_control_get_exclusive_by_index(
}
/**
* of_reset_control_get_shared_by_index - Lookup and obtain an shared
* of_reset_control_get_shared_by_index - Lookup and obtain a shared
* reference to a reset controller
* by index.
* @node: device to be reset by the controller
@ -322,7 +329,7 @@ devm_reset_control_get_exclusive_by_index(struct device *dev, int index)
/**
* devm_reset_control_get_shared_by_index - resource managed
* reset_control_get_shared
* reset_control_get_shared
* @dev: device to be reset by the controller
* @index: index of the reset controller
*