drm/i915: Simplify skl_max_scale()
Now that the planes declare their minimum cdclk requirements properly we don't need to check the cdclk in skl_max_scale() anymore. Just check against the maximum downscale ratio, and move the code next to it's only caller. v2: Add a comment explaining the HQ vs. not thing Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191015193035.25982-7-ville.syrjala@linux.intel.com
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3 changed files with 17 additions and 41 deletions
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@ -15145,44 +15145,6 @@ intel_cleanup_plane_fb(struct drm_plane *plane,
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intel_plane_unpin_fb(old_plane_state);
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intel_plane_unpin_fb(old_plane_state);
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}
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}
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int
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skl_max_scale(const struct intel_crtc_state *crtc_state,
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const struct drm_format_info *format)
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{
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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int max_scale;
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int crtc_clock, max_dotclk, tmpclk1, tmpclk2;
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if (!crtc_state->base.enable)
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return DRM_PLANE_HELPER_NO_SCALING;
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crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
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max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk;
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if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10)
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max_dotclk *= 2;
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if (WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock))
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return DRM_PLANE_HELPER_NO_SCALING;
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/*
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* skl max scale is lower of:
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* close to 3 but not 3, -1 is for that purpose
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* or
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* cdclk/crtc_clock
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*/
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if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv) ||
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!drm_format_info_is_yuv_semiplanar(format))
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tmpclk1 = 0x30000 - 1;
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else
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tmpclk1 = 0x20000 - 1;
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tmpclk2 = (1 << 8) * ((max_dotclk << 8) / crtc_clock);
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max_scale = min(tmpclk1, tmpclk2);
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return max_scale;
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}
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/**
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/**
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* intel_plane_destroy - destroy a plane
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* intel_plane_destroy - destroy a plane
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* @plane: plane to destroy
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* @plane: plane to destroy
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@ -563,8 +563,6 @@ void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
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u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_center);
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u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_center);
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int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
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int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
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int skl_max_scale(const struct intel_crtc_state *crtc_state,
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const struct drm_format_info *format);
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u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
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u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
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const struct intel_plane_state *plane_state);
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const struct intel_plane_state *plane_state);
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u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state);
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u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state);
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@ -2120,6 +2120,22 @@ static int skl_plane_check_nv12_rotation(const struct intel_plane_state *plane_s
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return 0;
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return 0;
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}
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}
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static int skl_plane_max_scale(struct drm_i915_private *dev_priv,
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const struct drm_framebuffer *fb)
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{
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/*
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* We don't yet know the final source width nor
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* whether we can use the HQ scaler mode. Assume
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* the best case.
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* FIXME need to properly check this later.
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*/
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if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv) ||
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!drm_format_info_is_yuv_semiplanar(fb->format))
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return 0x30000 - 1;
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else
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return 0x20000 - 1;
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}
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static int skl_plane_check(struct intel_crtc_state *crtc_state,
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static int skl_plane_check(struct intel_crtc_state *crtc_state,
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struct intel_plane_state *plane_state)
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struct intel_plane_state *plane_state)
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{
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{
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@ -2137,7 +2153,7 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state,
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/* use scaler when colorkey is not required */
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/* use scaler when colorkey is not required */
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if (!plane_state->ckey.flags && intel_fb_scalable(fb)) {
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if (!plane_state->ckey.flags && intel_fb_scalable(fb)) {
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min_scale = 1;
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min_scale = 1;
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max_scale = skl_max_scale(crtc_state, fb->format);
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max_scale = skl_plane_max_scale(dev_priv, fb);
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}
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}
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ret = drm_atomic_helper_check_plane_state(&plane_state->base,
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ret = drm_atomic_helper_check_plane_state(&plane_state->base,
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