powerpc/virtex: add dts file for ML507 reference design
This new file adds support for the ML507 reference design. The ML507 uses the Virtex 5 FXT FPGA which embeds a ppc440 core. Signed-off-by: John Linn <john.linn@xilinx.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
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John Linn
Grant Likely
parent
f3e909c275
commit
dc568ec490
1 changed files with 238 additions and 0 deletions
238
arch/powerpc/boot/dts/virtex440-ml507.dts
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238
arch/powerpc/boot/dts/virtex440-ml507.dts
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/*
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* This file supports the Xilinx ML507 board with the 440 processor.
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* A reference design for the FPGA is provided at http://git.xilinx.com.
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*
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* (C) Copyright 2008 Xilinx, Inc.
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "xlnx,virtex440";
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dcr-parent = <&ppc440_virtex5_0>;
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model = "testing";
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chosen {
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bootargs = "console=ttyS0 ip=on root=/dev/ram";
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linux,stdout-path = "/plb@0/serial@d0000000";
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} ;
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cpus {
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#address-cells = <1>;
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#cpus = <1>;
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#size-cells = <0>;
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ppc440_virtex5_0: cpu@0 {
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clock-frequency = <17d78400>;
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compatible = "PowerPC,440", "ibm,ppc440";
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d-cache-line-size = <20>;
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d-cache-size = <8000>;
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dcr-access-method = "native";
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dcr-controller ;
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device_type = "cpu";
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i-cache-line-size = <20>;
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i-cache-size = <8000>;
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model = "PowerPC,440";
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reg = <0>;
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timebase-frequency = <17d78400>;
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xlnx,apu-control = <1>;
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xlnx,apu-udi-0 = <c07701>;
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xlnx,apu-udi-1 = <c47701>;
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xlnx,apu-udi-10 = <0>;
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xlnx,apu-udi-11 = <0>;
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xlnx,apu-udi-12 = <0>;
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xlnx,apu-udi-13 = <0>;
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xlnx,apu-udi-14 = <0>;
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xlnx,apu-udi-15 = <0>;
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xlnx,apu-udi-2 = <0>;
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xlnx,apu-udi-3 = <0>;
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xlnx,apu-udi-4 = <0>;
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xlnx,apu-udi-5 = <0>;
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xlnx,apu-udi-6 = <0>;
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xlnx,apu-udi-7 = <0>;
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xlnx,apu-udi-8 = <0>;
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xlnx,apu-udi-9 = <0>;
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xlnx,dcr-autolock-enable = <1>;
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xlnx,dcu-rd-ld-cache-plb-prio = <0>;
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xlnx,dcu-rd-noncache-plb-prio = <0>;
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xlnx,dcu-rd-touch-plb-prio = <0>;
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xlnx,dcu-rd-urgent-plb-prio = <0>;
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xlnx,dcu-wr-flush-plb-prio = <0>;
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xlnx,dcu-wr-store-plb-prio = <0>;
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xlnx,dcu-wr-urgent-plb-prio = <0>;
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xlnx,dma0-control = <0>;
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xlnx,dma0-plb-prio = <0>;
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xlnx,dma0-rxchannelctrl = <1010000>;
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xlnx,dma0-rxirqtimer = <3ff>;
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xlnx,dma0-txchannelctrl = <1010000>;
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xlnx,dma0-txirqtimer = <3ff>;
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xlnx,dma1-control = <0>;
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xlnx,dma1-plb-prio = <0>;
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xlnx,dma1-rxchannelctrl = <1010000>;
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xlnx,dma1-rxirqtimer = <3ff>;
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xlnx,dma1-txchannelctrl = <1010000>;
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xlnx,dma1-txirqtimer = <3ff>;
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xlnx,dma2-control = <0>;
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xlnx,dma2-plb-prio = <0>;
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xlnx,dma2-rxchannelctrl = <1010000>;
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xlnx,dma2-rxirqtimer = <3ff>;
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xlnx,dma2-txchannelctrl = <1010000>;
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xlnx,dma2-txirqtimer = <3ff>;
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xlnx,dma3-control = <0>;
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xlnx,dma3-plb-prio = <0>;
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xlnx,dma3-rxchannelctrl = <1010000>;
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xlnx,dma3-rxirqtimer = <3ff>;
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xlnx,dma3-txchannelctrl = <1010000>;
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xlnx,dma3-txirqtimer = <3ff>;
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xlnx,endian-reset = <0>;
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xlnx,generate-plb-timespecs = <1>;
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xlnx,icu-rd-fetch-plb-prio = <0>;
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xlnx,icu-rd-spec-plb-prio = <0>;
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xlnx,icu-rd-touch-plb-prio = <0>;
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xlnx,interconnect-imask = <ffffffff>;
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xlnx,mplb-allow-lock-xfer = <1>;
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xlnx,mplb-arb-mode = <0>;
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xlnx,mplb-awidth = <20>;
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xlnx,mplb-counter = <500>;
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xlnx,mplb-dwidth = <80>;
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xlnx,mplb-max-burst = <8>;
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xlnx,mplb-native-dwidth = <80>;
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xlnx,mplb-p2p = <0>;
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xlnx,mplb-prio-dcur = <2>;
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xlnx,mplb-prio-dcuw = <3>;
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xlnx,mplb-prio-icu = <4>;
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xlnx,mplb-prio-splb0 = <1>;
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xlnx,mplb-prio-splb1 = <0>;
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xlnx,mplb-read-pipe-enable = <1>;
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xlnx,mplb-sync-tattribute = <0>;
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xlnx,mplb-wdog-enable = <1>;
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xlnx,mplb-write-pipe-enable = <1>;
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xlnx,mplb-write-post-enable = <1>;
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xlnx,num-dma = <1>;
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xlnx,pir = <f>;
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xlnx,ppc440mc-addr-base = <0>;
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xlnx,ppc440mc-addr-high = <1fffffff>;
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xlnx,ppc440mc-arb-mode = <0>;
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xlnx,ppc440mc-bank-conflict-mask = <c00000>;
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xlnx,ppc440mc-control = <f810008f>;
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xlnx,ppc440mc-max-burst = <8>;
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xlnx,ppc440mc-prio-dcur = <2>;
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xlnx,ppc440mc-prio-dcuw = <3>;
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xlnx,ppc440mc-prio-icu = <4>;
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xlnx,ppc440mc-prio-splb0 = <1>;
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xlnx,ppc440mc-prio-splb1 = <0>;
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xlnx,ppc440mc-row-conflict-mask = <3ffe00>;
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xlnx,ppcdm-asyncmode = <0>;
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xlnx,ppcds-asyncmode = <0>;
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xlnx,user-reset = <0>;
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DMA0: sdma@80 {
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compatible = "xlnx,ll-dma-1.00.a";
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dcr-reg = < 80 11 >;
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interrupt-parent = <&opb_intc_0>;
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interrupts = < 5 2 6 2 >;
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} ;
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} ;
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} ;
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plb_v46_cfb_0: plb@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "xlnx,plb-v46-1.02.a";
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ranges ;
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iic_bus: i2c@d0020000 {
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compatible = "xlnx,xps-iic-2.00.a";
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interrupt-parent = <&opb_intc_0>;
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interrupts = < 7 2 >;
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reg = < d0020000 200 >;
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xlnx,clk-freq = <5f5e100>;
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xlnx,family = "virtex5";
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xlnx,gpo-width = <1>;
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xlnx,iic-freq = <186a0>;
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xlnx,scl-inertial-delay = <0>;
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xlnx,sda-inertial-delay = <0>;
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xlnx,ten-bit-adr = <0>;
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} ;
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leds_8bit: gpio@d0010200 {
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compatible = "xlnx,xps-gpio-1.00.a";
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interrupt-parent = <&opb_intc_0>;
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interrupts = < 1 2 >;
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reg = < d0010200 200 >;
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xlnx,all-inputs = <0>;
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xlnx,all-inputs-2 = <0>;
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xlnx,dout-default = <0>;
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xlnx,dout-default-2 = <0>;
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xlnx,family = "virtex5";
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xlnx,gpio-width = <8>;
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xlnx,interrupt-present = <1>;
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xlnx,is-bidir = <1>;
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xlnx,is-bidir-2 = <1>;
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xlnx,is-dual = <0>;
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xlnx,tri-default = <ffffffff>;
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xlnx,tri-default-2 = <ffffffff>;
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} ;
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ll_temac_0: xps-ll-temac@91200000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "xlnx,compound";
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ethernet@91200000 {
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compatible = "xlnx,xps-ll-temac-1.01.a";
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device_type = "network";
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interrupt-parent = <&opb_intc_0>;
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interrupts = < 4 2 >;
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llink-connected = <&DMA0>;
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local-mac-address = [ 02 00 00 00 00 00 ];
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reg = < 91200000 40 >;
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xlnx,bus2core-clk-ratio = <1>;
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xlnx,phy-type = <1>;
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xlnx,phyaddr = <1>;
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xlnx,rxcsum = <0>;
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xlnx,rxfifo = <4000>;
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xlnx,temac-type = <0>;
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xlnx,txcsum = <0>;
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xlnx,txfifo = <4000>;
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} ;
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} ;
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opb_intc_0: interrupt-controller@d0020200 {
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#interrupt-cells = <2>;
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compatible = "xlnx,xps-intc-1.00.a";
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interrupt-controller ;
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reg = < d0020200 20 >;
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xlnx,num-intr-inputs = <8>;
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} ;
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plb_bram_if_cntlr_0: xps-bram-if-cntlr@ffff0000 {
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compatible = "xlnx,xps-bram-if-cntlr-1.00.a";
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reg = < ffff0000 10000 >;
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xlnx,family = "virtex5";
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} ;
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plb_bram_if_cntlr_1: xps-bram-if-cntlr@eee00000 {
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compatible = "xlnx,xps-bram-if-cntlr-1.00.a";
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reg = < eee00000 2000 >;
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xlnx,family = "virtex5";
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} ;
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rs232_uart_0: serial@d0000000 {
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clock-frequency = <1312d00>;
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compatible = "xlnx,xps-uart16550-2.00.a", "ns16550";
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current-speed = <2580>;
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device_type = "serial";
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interrupt-parent = <&opb_intc_0>;
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interrupts = < 0 2 >;
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reg = < d0000000 2000 >;
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reg-offset = <1003>;
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reg-shift = <2>;
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xlnx,family = "virtex5";
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xlnx,has-external-rclk = <0>;
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xlnx,has-external-xin = <1>;
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xlnx,is-a-16550 = <1>;
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} ;
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sysace_compactflash: sysace@d0030100 {
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compatible = "xlnx,xps-sysace-1.00.a";
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reg = < d0030100 80 >;
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xlnx,family = "virtex5";
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xlnx,mem-width = <10>;
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} ;
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} ;
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ppc440mc_ddr2_0: memory@0 {
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device_type = "memory";
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reg = < 0 20000000 >;
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} ;
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} ;
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