clk: tegra: pll: Add specialized logic for Tegra210
On Tegra210 SoC's, the logic to enable several of the plls is different from previous generations. Therefore, add registration functions specific to Tegra210 which will handle them appropriately. Reviewed-by: Benson Leung <bleung@chromium.org> Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Rhyland Klein
Thierry Reding
parent
267b62a969
commit
dd322f047d
2 changed files with 346 additions and 2 deletions
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@ -65,6 +65,7 @@
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#define PLLE_BASE_DIVN_WIDTH 8
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#define PLLE_BASE_DIVM_SHIFT 0
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#define PLLE_BASE_DIVM_WIDTH 8
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#define PLLE_BASE_ENABLE BIT(31)
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#define PLLE_MISC_SETUP_BASE_SHIFT 16
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#define PLLE_MISC_SETUP_BASE_MASK (0xffff << PLLE_MISC_SETUP_BASE_SHIFT)
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@ -102,6 +103,7 @@
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#define PLLE_AUX_SEQ_ENABLE BIT(24)
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#define PLLE_AUX_SEQ_START_STATE BIT(25)
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#define PLLE_AUX_PLLRE_SEL BIT(28)
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#define PLLE_AUX_SS_SEQ_INCLUDE BIT(31)
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#define XUSBIO_PLL_CFG0 0x51c
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#define XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0)
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@ -967,7 +969,8 @@ static int _calc_dynamic_ramp_rate(struct clk_hw *hw,
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#if defined(CONFIG_ARCH_TEGRA_114_SOC) || \
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defined(CONFIG_ARCH_TEGRA_124_SOC) || \
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defined(CONFIG_ARCH_TEGRA_132_SOC)
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defined(CONFIG_ARCH_TEGRA_132_SOC) || \
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defined(CONFIG_ARCH_TEGRA_210_SOC)
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u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate)
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{
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@ -1555,7 +1558,8 @@ struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
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#if defined(CONFIG_ARCH_TEGRA_114_SOC) || \
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defined(CONFIG_ARCH_TEGRA_124_SOC) || \
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defined(CONFIG_ARCH_TEGRA_132_SOC)
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defined(CONFIG_ARCH_TEGRA_132_SOC) || \
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defined(CONFIG_ARCH_TEGRA_210_SOC)
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static const struct clk_ops tegra_clk_pllxc_ops = {
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.is_enabled = clk_pll_is_enabled,
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.enable = clk_pll_enable,
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@ -1925,3 +1929,319 @@ struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name,
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return clk;
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}
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#endif
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#if defined(CONFIG_ARCH_TEGRA_210_SOC)
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static int clk_plle_tegra210_enable(struct clk_hw *hw)
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{
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struct tegra_clk_pll *pll = to_clk_pll(hw);
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struct tegra_clk_pll_freq_table sel;
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u32 val;
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int ret;
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unsigned long flags = 0;
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unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk));
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if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
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return -EINVAL;
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if (pll->lock)
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spin_lock_irqsave(pll->lock, flags);
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val = pll_readl_base(pll);
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val &= ~BIT(30); /* Disable lock override */
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pll_writel_base(val, pll);
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val = pll_readl(pll->params->aux_reg, pll);
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val |= PLLE_AUX_ENABLE_SWCTL;
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val &= ~PLLE_AUX_SEQ_ENABLE;
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pll_writel(val, pll->params->aux_reg, pll);
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udelay(1);
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val = pll_readl_misc(pll);
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val |= PLLE_MISC_LOCK_ENABLE;
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val |= PLLE_MISC_IDDQ_SW_CTRL;
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val &= ~PLLE_MISC_IDDQ_SW_VALUE;
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val |= PLLE_MISC_PLLE_PTS;
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val |= PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK;
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pll_writel_misc(val, pll);
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udelay(5);
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val = pll_readl(PLLE_SS_CTRL, pll);
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val |= PLLE_SS_DISABLE;
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pll_writel(val, PLLE_SS_CTRL, pll);
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val = pll_readl_base(pll);
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val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |
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divm_mask_shifted(pll));
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val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT);
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val |= sel.m << divm_shift(pll);
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val |= sel.n << divn_shift(pll);
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val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
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pll_writel_base(val, pll);
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udelay(1);
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val = pll_readl_base(pll);
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val |= PLLE_BASE_ENABLE;
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pll_writel_base(val, pll);
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ret = clk_pll_wait_for_lock(pll);
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if (ret < 0)
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goto out;
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val = pll_readl(PLLE_SS_CTRL, pll);
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val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT);
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val &= ~PLLE_SS_COEFFICIENTS_MASK;
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val |= PLLE_SS_COEFFICIENTS_VAL;
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pll_writel(val, PLLE_SS_CTRL, pll);
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val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS);
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pll_writel(val, PLLE_SS_CTRL, pll);
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udelay(1);
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val &= ~PLLE_SS_CNTL_INTERP_RESET;
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pll_writel(val, PLLE_SS_CTRL, pll);
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udelay(1);
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val = pll_readl_misc(pll);
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val &= ~PLLE_MISC_IDDQ_SW_CTRL;
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pll_writel_misc(val, pll);
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val = pll_readl(pll->params->aux_reg, pll);
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val |= (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SS_SEQ_INCLUDE);
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val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL);
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pll_writel(val, pll->params->aux_reg, pll);
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udelay(1);
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val |= PLLE_AUX_SEQ_ENABLE;
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pll_writel(val, pll->params->aux_reg, pll);
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out:
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if (pll->lock)
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spin_unlock_irqrestore(pll->lock, flags);
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return ret;
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}
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static void clk_plle_tegra210_disable(struct clk_hw *hw)
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{
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struct tegra_clk_pll *pll = to_clk_pll(hw);
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unsigned long flags = 0;
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u32 val;
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if (pll->lock)
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spin_lock_irqsave(pll->lock, flags);
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val = pll_readl_base(pll);
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val &= ~PLLE_BASE_ENABLE;
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pll_writel_base(val, pll);
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val = pll_readl_misc(pll);
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val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE;
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pll_writel_misc(val, pll);
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udelay(1);
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if (pll->lock)
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spin_unlock_irqrestore(pll->lock, flags);
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}
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static int clk_plle_tegra210_is_enabled(struct clk_hw *hw)
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{
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struct tegra_clk_pll *pll = to_clk_pll(hw);
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u32 val;
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val = pll_readl_base(pll);
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return val & PLLE_BASE_ENABLE ? 1 : 0;
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}
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static const struct clk_ops tegra_clk_plle_tegra210_ops = {
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.is_enabled = clk_plle_tegra210_is_enabled,
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.enable = clk_plle_tegra210_enable,
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.disable = clk_plle_tegra210_disable,
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.recalc_rate = clk_pll_recalc_rate,
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};
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struct clk *tegra_clk_register_plle_tegra210(const char *name,
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const char *parent_name,
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void __iomem *clk_base, unsigned long flags,
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struct tegra_clk_pll_params *pll_params,
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spinlock_t *lock)
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{
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struct tegra_clk_pll *pll;
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struct clk *clk;
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u32 val, val_aux;
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pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
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if (IS_ERR(pll))
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return ERR_CAST(pll);
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/* ensure parent is set to pll_re_vco */
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val = pll_readl_base(pll);
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val_aux = pll_readl(pll_params->aux_reg, pll);
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if (val & PLLE_BASE_ENABLE) {
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if ((val_aux & PLLE_AUX_PLLRE_SEL) ||
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(val_aux & PLLE_AUX_PLLP_SEL))
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WARN(1, "pll_e enabled with unsupported parent %s\n",
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(val_aux & PLLE_AUX_PLLP_SEL) ? "pllp_out0" :
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"pll_re_vco");
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} else {
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val_aux &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL);
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pll_writel(val_aux, pll_params->aux_reg, pll);
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}
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clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
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&tegra_clk_plle_tegra210_ops);
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if (IS_ERR(clk))
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kfree(pll);
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return clk;
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}
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struct clk *tegra_clk_register_pllc_tegra210(const char *name,
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const char *parent_name, void __iomem *clk_base,
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void __iomem *pmc, unsigned long flags,
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struct tegra_clk_pll_params *pll_params,
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spinlock_t *lock)
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{
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struct clk *parent, *clk;
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const struct pdiv_map *p_tohw = pll_params->pdiv_tohw;
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struct tegra_clk_pll *pll;
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unsigned long parent_rate;
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if (!p_tohw)
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return ERR_PTR(-EINVAL);
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parent = __clk_lookup(parent_name);
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if (!parent) {
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WARN(1, "parent clk %s of %s must be registered first\n",
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name, parent_name);
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return ERR_PTR(-EINVAL);
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}
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parent_rate = clk_get_rate(parent);
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pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
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pll_params->flags |= TEGRA_PLL_BYPASS;
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pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
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if (IS_ERR(pll))
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return ERR_CAST(pll);
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clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
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&tegra_clk_pll_ops);
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if (IS_ERR(clk))
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kfree(pll);
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return clk;
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}
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struct clk *tegra_clk_register_pllxc_tegra210(const char *name,
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const char *parent_name, void __iomem *clk_base,
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void __iomem *pmc, unsigned long flags,
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struct tegra_clk_pll_params *pll_params,
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spinlock_t *lock)
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{
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struct tegra_clk_pll *pll;
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struct clk *clk, *parent;
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unsigned long parent_rate;
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parent = __clk_lookup(parent_name);
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if (!parent) {
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WARN(1, "parent clk %s of %s must be registered first\n",
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name, parent_name);
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return ERR_PTR(-EINVAL);
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}
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if (!pll_params->pdiv_tohw)
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return ERR_PTR(-EINVAL);
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parent_rate = clk_get_rate(parent);
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pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
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pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
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if (IS_ERR(pll))
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return ERR_CAST(pll);
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clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
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&tegra_clk_pll_ops);
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if (IS_ERR(clk))
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kfree(pll);
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return clk;
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}
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struct clk *tegra_clk_register_pllss_tegra210(const char *name,
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const char *parent_name, void __iomem *clk_base,
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unsigned long flags,
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struct tegra_clk_pll_params *pll_params,
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spinlock_t *lock)
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{
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struct tegra_clk_pll *pll;
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struct clk *clk, *parent;
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struct tegra_clk_pll_freq_table cfg;
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unsigned long parent_rate;
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u32 val;
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int i;
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if (!pll_params->div_nmp)
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return ERR_PTR(-EINVAL);
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parent = __clk_lookup(parent_name);
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if (!parent) {
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WARN(1, "parent clk %s of %s must be registered first\n",
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name, parent_name);
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return ERR_PTR(-EINVAL);
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}
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pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
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if (IS_ERR(pll))
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return ERR_CAST(pll);
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val = pll_readl_base(pll);
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val &= ~PLLSS_REF_SRC_SEL_MASK;
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pll_writel_base(val, pll);
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parent_rate = clk_get_rate(parent);
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pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
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/* initialize PLL to minimum rate */
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cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);
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cfg.n = cfg.m * pll_params->vco_min / parent_rate;
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for (i = 0; pll_params->pdiv_tohw[i].pdiv; i++)
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;
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if (!i) {
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kfree(pll);
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return ERR_PTR(-EINVAL);
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}
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cfg.p = pll_params->pdiv_tohw[i-1].hw_val;
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_update_pll_mnp(pll, &cfg);
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pll_writel_misc(PLLSS_MISC_DEFAULT, pll);
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val = pll_readl_base(pll);
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if (val & PLL_BASE_ENABLE) {
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if (val & BIT(pll_params->iddq_bit_idx)) {
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WARN(1, "%s is on but IDDQ set\n", name);
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kfree(pll);
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return ERR_PTR(-EINVAL);
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}
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} else
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val |= BIT(pll_params->iddq_bit_idx);
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val &= ~PLLSS_LOCK_OVERRIDE;
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pll_writel_base(val, pll);
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clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
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&tegra_clk_pll_ops);
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if (IS_ERR(clk))
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kfree(pll);
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return clk;
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}
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#endif
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@ -334,6 +334,12 @@ struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name,
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struct tegra_clk_pll_params *pll_params,
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spinlock_t *lock);
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struct clk *tegra_clk_register_pllxc_tegra210(const char *name,
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const char *parent_name, void __iomem *clk_base,
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void __iomem *pmc, unsigned long flags,
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struct tegra_clk_pll_params *pll_params,
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spinlock_t *lock);
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struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name,
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void __iomem *clk_base, void __iomem *pmc,
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unsigned long flags,
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@ -358,6 +364,24 @@ struct clk *tegra_clk_register_plle_tegra114(const char *name,
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struct tegra_clk_pll_params *pll_params,
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spinlock_t *lock);
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struct clk *tegra_clk_register_plle_tegra210(const char *name,
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const char *parent_name,
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void __iomem *clk_base, unsigned long flags,
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struct tegra_clk_pll_params *pll_params,
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spinlock_t *lock);
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struct clk *tegra_clk_register_pllc_tegra210(const char *name,
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const char *parent_name, void __iomem *clk_base,
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void __iomem *pmc, unsigned long flags,
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struct tegra_clk_pll_params *pll_params,
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spinlock_t *lock);
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struct clk *tegra_clk_register_pllss_tegra210(const char *name,
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const char *parent_name, void __iomem *clk_base,
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unsigned long flags,
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struct tegra_clk_pll_params *pll_params,
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spinlock_t *lock);
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struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name,
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void __iomem *clk_base, unsigned long flags,
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struct tegra_clk_pll_params *pll_params,
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