sparc64: Fix Niagara2 perf event handling.
For chips like Niagara2 that have true overflow indications in the %pcr (which we don't actually need and don't use) the interrupt signal persists until the overflow bits are cleared by an explicit %pcr write. Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -986,6 +986,17 @@ static int __kprobes perf_event_nmi_handler(struct notifier_block *self,
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data.addr = 0;
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cpuc = &__get_cpu_var(cpu_hw_events);
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/* If the PMU has the TOE IRQ enable bits, we need to do a
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* dummy write to the %pcr to clear the overflow bits and thus
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* the interrupt.
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*
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* Do this before we peek at the counters to determine
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* overflow so we don't lose any events.
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*/
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if (sparc_pmu->irq_bit)
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pcr_ops->write(cpuc->pcr);
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for (idx = 0; idx < MAX_HWEVENTS; idx++) {
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struct perf_event *event = cpuc->events[idx];
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struct hw_perf_event *hwc;
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