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clk: gxbb: expose MPLL2 clock for use by DT

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This exposes the MPLL2 clock as this is one of the input clocks of the
ethernet controller's internal mux.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
This commit is contained in:
Martin Blumenstingl 2016-09-06 23:38:44 +02:00 committed by Kevin Hilman
parent dcdcc66022
commit ed6f4b5180
2 changed files with 2 additions and 1 deletions
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2
drivers/clk/meson/gxbb.h
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@ -183,7 +183,7 @@
/* CLKID_CLK81 */
#define CLKID_MPLL0 13
#define CLKID_MPLL1 14
#define CLKID_MPLL2 15
/* CLKID_MPLL2 */
#define CLKID_DDR 16
#define CLKID_DOS 17
#define CLKID_ISA 18

1
include/dt-bindings/clock/gxbb-clkc.h
View file

@ -11,6 +11,7 @@
#define CLKID_FCLK_DIV3 5
#define CLKID_FCLK_DIV4 6
#define CLKID_CLK81 12
#define CLKID_MPLL2 15
#define CLKID_ETH 36
#define CLKID_SD_EMMC_A 94
#define CLKID_SD_EMMC_B 95