clk: zte: add audio clocks for zx296718
The audio related clock support is missing from the existing zx296718 clock driver. Let's add it, so that the upstream ZX SPDIF driver can work for HDMI audio support. Signed-off-by: Jun Nie <jun.nie@linaro.org> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> [sboyd@codeaurora.org: Staticize some more structures] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This commit is contained in:
Jun Nie
Stephen Boyd
parent
6999027605
commit
edc6da239a
3 changed files with 275 additions and 0 deletions
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@ -897,10 +897,137 @@ static int __init lsp1_clocks_init(struct device_node *np)
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return 0;
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}
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PNAME(audio_wclk_common_p) = {
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"audio_99m",
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"audio_24m",
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};
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PNAME(audio_timer_p) = {
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"audio_24m",
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"audio_32k",
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};
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static struct zx_clk_mux audio_mux_clk[] = {
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MUX(0, "i2s0_wclk_mux", audio_wclk_common_p, AUDIO_I2S0_CLK, 0, 1),
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MUX(0, "i2s1_wclk_mux", audio_wclk_common_p, AUDIO_I2S1_CLK, 0, 1),
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MUX(0, "i2s2_wclk_mux", audio_wclk_common_p, AUDIO_I2S2_CLK, 0, 1),
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MUX(0, "i2s3_wclk_mux", audio_wclk_common_p, AUDIO_I2S3_CLK, 0, 1),
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MUX(0, "i2c0_wclk_mux", audio_wclk_common_p, AUDIO_I2C0_CLK, 0, 1),
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MUX(0, "spdif0_wclk_mux", audio_wclk_common_p, AUDIO_SPDIF0_CLK, 0, 1),
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MUX(0, "spdif1_wclk_mux", audio_wclk_common_p, AUDIO_SPDIF1_CLK, 0, 1),
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MUX(0, "timer_wclk_mux", audio_timer_p, AUDIO_TIMER_CLK, 0, 1),
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};
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static struct clk_zx_audio_divider audio_adiv_clk[] = {
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AUDIO_DIV(0, "i2s0_wclk_div", "i2s0_wclk_mux", AUDIO_I2S0_DIV_CFG1),
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AUDIO_DIV(0, "i2s1_wclk_div", "i2s1_wclk_mux", AUDIO_I2S1_DIV_CFG1),
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AUDIO_DIV(0, "i2s2_wclk_div", "i2s2_wclk_mux", AUDIO_I2S2_DIV_CFG1),
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AUDIO_DIV(0, "i2s3_wclk_div", "i2s3_wclk_mux", AUDIO_I2S3_DIV_CFG1),
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AUDIO_DIV(0, "spdif0_wclk_div", "spdif0_wclk_mux", AUDIO_SPDIF0_DIV_CFG1),
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AUDIO_DIV(0, "spdif1_wclk_div", "spdif1_wclk_mux", AUDIO_SPDIF1_DIV_CFG1),
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};
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static struct zx_clk_div audio_div_clk[] = {
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DIV_T(0, "tdm_wclk_div", "audio_16m384", AUDIO_TDM_CLK, 8, 4, 0, common_div_table),
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};
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static struct zx_clk_gate audio_gate_clk[] = {
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GATE(AUDIO_I2S0_WCLK, "i2s0_wclk", "i2s0_wclk_div", AUDIO_I2S0_CLK, 9, CLK_SET_RATE_PARENT, 0),
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GATE(AUDIO_I2S1_WCLK, "i2s1_wclk", "i2s1_wclk_div", AUDIO_I2S1_CLK, 9, CLK_SET_RATE_PARENT, 0),
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GATE(AUDIO_I2S2_WCLK, "i2s2_wclk", "i2s2_wclk_div", AUDIO_I2S2_CLK, 9, CLK_SET_RATE_PARENT, 0),
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GATE(AUDIO_I2S3_WCLK, "i2s3_wclk", "i2s3_wclk_div", AUDIO_I2S3_CLK, 9, CLK_SET_RATE_PARENT, 0),
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GATE(AUDIO_I2C0_WCLK, "i2c0_wclk", "i2c0_wclk_mux", AUDIO_I2C0_CLK, 9, CLK_SET_RATE_PARENT, 0),
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GATE(AUDIO_SPDIF0_WCLK, "spdif0_wclk", "spdif0_wclk_div", AUDIO_SPDIF0_CLK, 9, CLK_SET_RATE_PARENT, 0),
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GATE(AUDIO_SPDIF1_WCLK, "spdif1_wclk", "spdif1_wclk_div", AUDIO_SPDIF1_CLK, 9, CLK_SET_RATE_PARENT, 0),
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GATE(AUDIO_TDM_WCLK, "tdm_wclk", "tdm_wclk_div", AUDIO_TDM_CLK, 17, CLK_SET_RATE_PARENT, 0),
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GATE(AUDIO_TS_PCLK, "tempsensor_pclk", "clk49m5", AUDIO_TS_CLK, 1, 0, 0),
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};
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static struct clk_hw_onecell_data audio_hw_onecell_data = {
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.num = AUDIO_NR_CLKS,
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.hws = {
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[AUDIO_NR_CLKS - 1] = NULL,
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},
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};
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static int __init audio_clocks_init(struct device_node *np)
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{
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void __iomem *reg_base;
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int i, ret;
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reg_base = of_iomap(np, 0);
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if (!reg_base) {
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pr_err("%s: Unable to map audio clk base\n", __func__);
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return -ENXIO;
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}
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for (i = 0; i < ARRAY_SIZE(audio_mux_clk); i++) {
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if (audio_mux_clk[i].id)
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audio_hw_onecell_data.hws[audio_mux_clk[i].id] =
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&audio_mux_clk[i].mux.hw;
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audio_mux_clk[i].mux.reg += (uintptr_t)reg_base;
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ret = clk_hw_register(NULL, &audio_mux_clk[i].mux.hw);
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if (ret) {
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pr_warn("audio clk %s init error!\n",
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audio_mux_clk[i].mux.hw.init->name);
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}
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}
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for (i = 0; i < ARRAY_SIZE(audio_adiv_clk); i++) {
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if (audio_adiv_clk[i].id)
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audio_hw_onecell_data.hws[audio_adiv_clk[i].id] =
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&audio_adiv_clk[i].hw;
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audio_adiv_clk[i].reg_base += (uintptr_t)reg_base;
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ret = clk_hw_register(NULL, &audio_adiv_clk[i].hw);
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if (ret) {
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pr_warn("audio clk %s init error!\n",
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audio_adiv_clk[i].hw.init->name);
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}
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}
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for (i = 0; i < ARRAY_SIZE(audio_div_clk); i++) {
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if (audio_div_clk[i].id)
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audio_hw_onecell_data.hws[audio_div_clk[i].id] =
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&audio_div_clk[i].div.hw;
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audio_div_clk[i].div.reg += (uintptr_t)reg_base;
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ret = clk_hw_register(NULL, &audio_div_clk[i].div.hw);
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if (ret) {
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pr_warn("audio clk %s init error!\n",
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audio_div_clk[i].div.hw.init->name);
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}
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}
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for (i = 0; i < ARRAY_SIZE(audio_gate_clk); i++) {
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if (audio_gate_clk[i].id)
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audio_hw_onecell_data.hws[audio_gate_clk[i].id] =
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&audio_gate_clk[i].gate.hw;
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audio_gate_clk[i].gate.reg += (uintptr_t)reg_base;
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ret = clk_hw_register(NULL, &audio_gate_clk[i].gate.hw);
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if (ret) {
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pr_warn("audio clk %s init error!\n",
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audio_gate_clk[i].gate.hw.init->name);
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}
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}
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ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get,
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&audio_hw_onecell_data);
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if (ret) {
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pr_err("failed to register audio clk provider: %d\n", ret);
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return ret;
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}
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return 0;
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}
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static const struct of_device_id zx_clkc_match_table[] = {
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{ .compatible = "zte,zx296718-topcrm", .data = &top_clocks_init },
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{ .compatible = "zte,zx296718-lsp0crm", .data = &lsp0_clocks_init },
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{ .compatible = "zte,zx296718-lsp1crm", .data = &lsp1_clocks_init },
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{ .compatible = "zte,zx296718-audiocrm", .data = &audio_clocks_init },
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{ }
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};
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@ -9,6 +9,7 @@
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#include <linux/clk-provider.h>
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#include <linux/err.h>
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#include <linux/gcd.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/slab.h>
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@ -310,3 +311,129 @@ struct clk *clk_register_zx_audio(const char *name,
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return clk;
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}
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#define CLK_AUDIO_DIV_FRAC BIT(0)
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#define CLK_AUDIO_DIV_INT BIT(1)
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#define CLK_AUDIO_DIV_UNCOMMON BIT(1)
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#define CLK_AUDIO_DIV_FRAC_NSHIFT 16
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#define CLK_AUDIO_DIV_INT_FRAC_RE BIT(16)
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#define CLK_AUDIO_DIV_INT_FRAC_MAX (0xffff)
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#define CLK_AUDIO_DIV_INT_FRAC_MIN (0x2)
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#define CLK_AUDIO_DIV_INT_INT_SHIFT 24
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#define CLK_AUDIO_DIV_INT_INT_WIDTH 4
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struct zx_clk_audio_div_table {
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unsigned long rate;
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unsigned int int_reg;
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unsigned int frac_reg;
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};
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#define to_clk_zx_audio_div(_hw) container_of(_hw, struct clk_zx_audio_divider, hw)
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static unsigned long audio_calc_rate(struct clk_zx_audio_divider *audio_div,
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u32 reg_frac, u32 reg_int,
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unsigned long parent_rate)
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{
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unsigned long rate, m, n;
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m = reg_frac & 0xffff;
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n = (reg_frac >> 16) & 0xffff;
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m = (reg_int & 0xffff) * n + m;
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rate = (parent_rate * n) / m;
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return rate;
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}
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static void audio_calc_reg(struct clk_zx_audio_divider *audio_div,
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struct zx_clk_audio_div_table *div_table,
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unsigned long rate, unsigned long parent_rate)
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{
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unsigned int reg_int, reg_frac;
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unsigned long m, n, div;
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reg_int = parent_rate / rate;
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if (reg_int > CLK_AUDIO_DIV_INT_FRAC_MAX)
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reg_int = CLK_AUDIO_DIV_INT_FRAC_MAX;
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else if (reg_int < CLK_AUDIO_DIV_INT_FRAC_MIN)
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reg_int = 0;
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m = parent_rate - rate * reg_int;
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n = rate;
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div = gcd(m, n);
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m = m / div;
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n = n / div;
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if ((m >> 16) || (n >> 16)) {
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if (m > n) {
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n = n * 0xffff / m;
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m = 0xffff;
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} else {
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m = m * 0xffff / n;
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n = 0xffff;
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}
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}
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reg_frac = m | (n << 16);
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div_table->rate = parent_rate * n / (reg_int * n + m);
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div_table->int_reg = reg_int;
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div_table->frac_reg = reg_frac;
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}
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static unsigned long zx_audio_div_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_zx_audio_divider *zx_audio_div = to_clk_zx_audio_div(hw);
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u32 reg_frac, reg_int;
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reg_frac = readl_relaxed(zx_audio_div->reg_base);
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reg_int = readl_relaxed(zx_audio_div->reg_base + 0x4);
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return audio_calc_rate(zx_audio_div, reg_frac, reg_int, parent_rate);
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}
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static long zx_audio_div_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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struct clk_zx_audio_divider *zx_audio_div = to_clk_zx_audio_div(hw);
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struct zx_clk_audio_div_table divt;
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audio_calc_reg(zx_audio_div, &divt, rate, *prate);
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return audio_calc_rate(zx_audio_div, divt.frac_reg, divt.int_reg, *prate);
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}
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static int zx_audio_div_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_zx_audio_divider *zx_audio_div = to_clk_zx_audio_div(hw);
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struct zx_clk_audio_div_table divt;
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unsigned int val;
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audio_calc_reg(zx_audio_div, &divt, rate, parent_rate);
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if (divt.rate != rate)
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pr_debug("the real rate is:%ld", divt.rate);
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writel_relaxed(divt.frac_reg, zx_audio_div->reg_base);
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val = readl_relaxed(zx_audio_div->reg_base + 0x4);
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val &= ~0xffff;
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val |= divt.int_reg | CLK_AUDIO_DIV_INT_FRAC_RE;
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writel_relaxed(val, zx_audio_div->reg_base + 0x4);
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mdelay(1);
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val = readl_relaxed(zx_audio_div->reg_base + 0x4);
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val &= ~CLK_AUDIO_DIV_INT_FRAC_RE;
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writel_relaxed(val, zx_audio_div->reg_base + 0x4);
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return 0;
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}
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const struct clk_ops zx_audio_div_ops = {
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.recalc_rate = zx_audio_div_recalc_rate,
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.round_rate = zx_audio_div_round_rate,
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.set_rate = zx_audio_div_set_rate,
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};
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@ -153,6 +153,25 @@ struct zx_clk_div {
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.id = _id, \
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}
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struct clk_zx_audio_divider {
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struct clk_hw hw;
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void __iomem *reg_base;
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unsigned int rate_count;
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spinlock_t *lock;
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u16 id;
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};
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#define AUDIO_DIV(_id, _name, _parent, _reg) \
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{ \
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.reg_base = (void __iomem *) _reg, \
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.lock = &clk_lock, \
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.hw.init = CLK_HW_INIT(_name, \
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_parent, \
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&zx_audio_div_ops, \
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0), \
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.id = _id, \
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}
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struct clk *clk_register_zx_pll(const char *name, const char *parent_name,
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unsigned long flags, void __iomem *reg_base,
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const struct zx_pll_config *lookup_table, int count, spinlock_t *lock);
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@ -167,4 +186,6 @@ struct clk *clk_register_zx_audio(const char *name,
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unsigned long flags, void __iomem *reg_base);
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extern const struct clk_ops zx_pll_ops;
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extern const struct clk_ops zx_audio_div_ops;
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#endif
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