[MIPS] cmbvr4133: Remove support
It cannot be built for a long time and nobody maintains it. Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Yoichi Yuasa
Ralf Baechle
parent
3f16654f36
commit
efff4ae259
11 changed files with 0 additions and 734 deletions
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@ -354,12 +354,6 @@ load-$(CONFIG_LASAT) += 0xffffffff80000000
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core-$(CONFIG_MACH_VR41XX) += arch/mips/vr41xx/common/
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cflags-$(CONFIG_MACH_VR41XX) += -Iinclude/asm-mips/mach-vr41xx
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#
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# NEC VR4133
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#
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core-$(CONFIG_NEC_CMBVR4133) += arch/mips/vr41xx/nec-cmbvr4133/
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load-$(CONFIG_NEC_CMBVR4133) += 0xffffffff80100000
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#
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# ZAO Networks Capcella (VR4131)
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#
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@ -13,7 +13,6 @@ obj-$(CONFIG_MIPS_MSC) += ops-msc.o
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obj-$(CONFIG_MIPS_NILE4) += ops-nile4.o
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obj-$(CONFIG_SOC_TX3927) += ops-tx3927.o
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obj-$(CONFIG_PCI_VR41XX) += ops-vr41xx.o pci-vr41xx.o
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obj-$(CONFIG_NEC_CMBVR4133) += fixup-vr4133.o
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obj-$(CONFIG_MARKEINS) += ops-emma2rh.o pci-emma2rh.o fixup-emma2rh.o
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obj-$(CONFIG_PCI_TX4927) += ops-tx4927.o
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@ -1,194 +0,0 @@
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/*
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* arch/mips/pci/fixup-vr4133.c
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*
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* The NEC CMB-VR4133 Board specific PCI fixups.
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*
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* Author: Yoichi Yuasa <yyuasa@mvista.com, or source@mvista.com> and
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* Alex Sapkov <asapkov@ru.mvista.com>
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*
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* 2003-2004 (c) MontaVista, Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*
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* Modified for support in 2.6
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* Author: Manish Lachwani (mlachwani@mvista.com)
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*
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*/
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/kernel.h>
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#include <asm/io.h>
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#include <asm/i8259.h>
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#include <asm/vr41xx/cmbvr4133.h>
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extern int vr4133_rockhopper;
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extern void ali_m1535plus_init(struct pci_dev *dev);
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extern void ali_m5229_init(struct pci_dev *dev);
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/* Do platform specific device initialization at pci_enable_device() time */
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int pcibios_plat_dev_init(struct pci_dev *dev)
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{
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/*
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* We have to reset AMD PCnet adapter on Rockhopper since
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* PMON leaves it enabled and generating interrupts. This leads
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* to a lock if some PCI device driver later enables the IRQ line
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* shared with PCnet and there is no AMD PCnet driver to catch its
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* interrupts.
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*/
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#ifdef CONFIG_ROCKHOPPER
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if (dev->vendor == PCI_VENDOR_ID_AMD &&
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dev->device == PCI_DEVICE_ID_AMD_LANCE) {
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inl(pci_resource_start(dev, 0) + 0x18);
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}
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#endif
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/*
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* we have to open the bridges' windows down to 0 because otherwise
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* we cannot access ISA south bridge I/O registers that get mapped from
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* 0. for example, 8259 PIC would be unaccessible without that
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*/
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if(dev->vendor == PCI_VENDOR_ID_INTEL && dev->device == PCI_DEVICE_ID_INTEL_S21152BB) {
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pci_write_config_byte(dev, PCI_IO_BASE, 0);
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if(dev->bus->number == 0) {
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pci_write_config_word(dev, PCI_IO_BASE_UPPER16, 0);
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} else {
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pci_write_config_word(dev, PCI_IO_BASE_UPPER16, 1);
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}
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}
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return 0;
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}
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/*
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* M1535 IRQ mapping
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* Feel free to change this, although it shouldn't be needed
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*/
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#define M1535_IRQ_INTA 7
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#define M1535_IRQ_INTB 9
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#define M1535_IRQ_INTC 10
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#define M1535_IRQ_INTD 11
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#define M1535_IRQ_USB 9
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#define M1535_IRQ_IDE 14
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#define M1535_IRQ_IDE2 15
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#define M1535_IRQ_PS2 12
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#define M1535_IRQ_RTC 8
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#define M1535_IRQ_FDC 6
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#define M1535_IRQ_AUDIO 5
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#define M1535_IRQ_COM1 4
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#define M1535_IRQ_COM2 4
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#define M1535_IRQ_IRDA 3
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#define M1535_IRQ_KBD 1
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#define M1535_IRQ_TMR 0
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/* Rockhopper "slots" assignment; this is hard-coded ... */
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#define ROCKHOPPER_M5451_SLOT 1
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#define ROCKHOPPER_M1535_SLOT 2
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#define ROCKHOPPER_M5229_SLOT 11
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#define ROCKHOPPER_M5237_SLOT 15
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#define ROCKHOPPER_PMU_SLOT 12
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/* ... and hard-wired. */
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#define ROCKHOPPER_PCI1_SLOT 3
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#define ROCKHOPPER_PCI2_SLOT 4
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#define ROCKHOPPER_PCI3_SLOT 5
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#define ROCKHOPPER_PCI4_SLOT 6
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#define ROCKHOPPER_PCNET_SLOT 1
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#define M1535_IRQ_MASK(n) (1 << (n))
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#define M1535_IRQ_EDGE (M1535_IRQ_MASK(M1535_IRQ_TMR) | \
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M1535_IRQ_MASK(M1535_IRQ_KBD) | \
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M1535_IRQ_MASK(M1535_IRQ_COM1) | \
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M1535_IRQ_MASK(M1535_IRQ_COM2) | \
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M1535_IRQ_MASK(M1535_IRQ_IRDA) | \
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M1535_IRQ_MASK(M1535_IRQ_RTC) | \
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M1535_IRQ_MASK(M1535_IRQ_FDC) | \
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M1535_IRQ_MASK(M1535_IRQ_PS2))
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#define M1535_IRQ_LEVEL (M1535_IRQ_MASK(M1535_IRQ_IDE) | \
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M1535_IRQ_MASK(M1535_IRQ_USB) | \
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M1535_IRQ_MASK(M1535_IRQ_INTA) | \
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M1535_IRQ_MASK(M1535_IRQ_INTB) | \
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M1535_IRQ_MASK(M1535_IRQ_INTC) | \
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M1535_IRQ_MASK(M1535_IRQ_INTD))
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struct irq_map_entry {
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u16 bus;
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u8 slot;
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u8 irq;
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};
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static struct irq_map_entry int_map[] = {
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{1, ROCKHOPPER_M5451_SLOT, M1535_IRQ_AUDIO}, /* Audio controller */
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{1, ROCKHOPPER_PCI1_SLOT, M1535_IRQ_INTD}, /* PCI slot #1 */
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{1, ROCKHOPPER_PCI2_SLOT, M1535_IRQ_INTC}, /* PCI slot #2 */
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{1, ROCKHOPPER_M5237_SLOT, M1535_IRQ_USB}, /* USB host controller */
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{1, ROCKHOPPER_M5229_SLOT, IDE_PRIMARY_IRQ}, /* IDE controller */
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{2, ROCKHOPPER_PCNET_SLOT, M1535_IRQ_INTD}, /* AMD Am79c973 on-board
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ethernet */
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{2, ROCKHOPPER_PCI3_SLOT, M1535_IRQ_INTB}, /* PCI slot #3 */
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{2, ROCKHOPPER_PCI4_SLOT, M1535_IRQ_INTC} /* PCI slot #4 */
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};
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static int pci_intlines[] =
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{ M1535_IRQ_INTA, M1535_IRQ_INTB, M1535_IRQ_INTC, M1535_IRQ_INTD };
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/* Determine the Rockhopper IRQ line number for the PCI device */
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int rockhopper_get_irq(struct pci_dev *dev, u8 pin, u8 slot)
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{
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struct pci_bus *bus;
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int i;
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bus = dev->bus;
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if (bus == NULL)
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return -1;
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for (i = 0; i < ARRAY_SIZE(int_map); i++) {
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if (int_map[i].bus == bus->number && int_map[i].slot == slot) {
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int line;
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for (line = 0; line < 4; line++)
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if (pci_intlines[line] == int_map[i].irq)
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break;
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if (line < 4)
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return pci_intlines[(line + (pin - 1)) % 4];
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else
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return int_map[i].irq;
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}
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}
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return -1;
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}
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#ifdef CONFIG_ROCKHOPPER
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void i8259_init(void)
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{
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init_i8259_irqs();
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outb(0x00, 0x4d0);
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outb(0x02, 0x4d1); /* USB IRQ9 is level */
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}
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#endif
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int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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{
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pci_probe_only = 1;
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#ifdef CONFIG_ROCKHOPPER
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if( dev->bus->number == 1 && vr4133_rockhopper ) {
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if(slot == ROCKHOPPER_PCI1_SLOT || slot == ROCKHOPPER_PCI2_SLOT)
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dev->irq = CMBVR41XX_INTA_IRQ;
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else
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dev->irq = rockhopper_get_irq(dev, pin, slot);
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} else
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dev->irq = CMBVR41XX_INTA_IRQ;
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#else
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dev->irq = CMBVR41XX_INTA_IRQ;
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#endif
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return dev->irq;
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, ali_m1535plus_init);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M5229, ali_m5229_init);
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@ -23,16 +23,6 @@ config IBM_WORKPAD
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select SYS_SUPPORTS_32BIT_KERNEL
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select SYS_SUPPORTS_LITTLE_ENDIAN
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config NEC_CMBVR4133
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bool "NEC CMB-VR4133"
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select CEVT_R4K
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select CSRC_R4K
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select DMA_NONCOHERENT
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select IRQ_CPU
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select HW_HAS_PCI
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select SYS_SUPPORTS_32BIT_KERNEL
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select SYS_SUPPORTS_LITTLE_ENDIAN
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config TANBAC_TB022X
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bool "TANBAC VR4131 multichip module and TANBAC VR4131DIMM"
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select CEVT_R4K
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@ -73,13 +63,6 @@ config ZAO_CAPCELLA
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endchoice
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config ROCKHOPPER
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bool "Support for Rockhopper base board"
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depends on NEC_CMBVR4133
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select PCI_VR41XX
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select I8259
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select HAVE_STD_PC_SERIAL_PORT
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choice
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prompt "Base board type"
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depends on TANBAC_TB022X
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@ -1,8 +0,0 @@
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#
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# Makefile for the NEC-CMBVR4133
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#
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obj-y := init.o setup.o
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obj-$(CONFIG_PCI) += m1535plus.o
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obj-$(CONFIG_ROCKHOPPER) += irq.o
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@ -1,65 +0,0 @@
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/*
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* arch/mips/vr41xx/nec-cmbvr4133/init.c
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*
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* PROM library initialisation code for NEC CMB-VR4133 board.
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*
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* Author: Yoichi Yuasa <yyuasa@mvista.com, or source@mvista.com> and
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* Jun Sun <jsun@mvista.com, or source@mvista.com> and
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* Alex Sapkov <asapkov@ru.mvista.com>
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*
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* 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*
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* Support for NEC-CMBVR4133 in 2.6
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* Manish Lachwani (mlachwani@mvista.com)
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*/
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#ifdef CONFIG_ROCKHOPPER
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#include <asm/io.h>
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#include <linux/pci.h>
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#define PCICONFDREG 0xaf000c14
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#define PCICONFAREG 0xaf000c18
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void disable_pcnet(void)
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{
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u32 data;
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/*
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* Workaround for the bug in PMON on VR4133. PMON leaves
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* AMD PCNet controller (on Rockhopper) initialized and running in
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* bus master mode. We have do disable it before doing any
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* further initialization. Or we get problems with PCI bus 2
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* and random lockups and crashes.
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*/
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writel((2 << 16) |
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(PCI_DEVFN(1, 0) << 8) |
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(0 & 0xfc) |
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1UL,
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PCICONFAREG);
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data = readl(PCICONFDREG);
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writel((2 << 16) |
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(PCI_DEVFN(1, 0) << 8) |
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(4 & 0xfc) |
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1UL,
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PCICONFAREG);
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data = readl(PCICONFDREG);
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writel((2 << 16) |
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(PCI_DEVFN(1, 0) << 8) |
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(4 & 0xfc) |
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1UL,
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PCICONFAREG);
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data &= ~4;
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writel(data, PCICONFDREG);
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}
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#endif
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@ -1,46 +0,0 @@
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/*
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* arch/mips/vr41xx/nec-cmbvr4133/irq.c
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*
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* Interrupt routines for the NEC CMB-VR4133 board.
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*
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* Author: Yoichi Yuasa <yyuasa@mvista.com, or source@mvista.com> and
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* Alex Sapkov <asapkov@ru.mvista.com>
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*
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* 2003-2004 (c) MontaVista, Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*
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* Support for NEC-CMBVR4133 in 2.6
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* Manish Lachwani (mlachwani@mvista.com)
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*/
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#include <linux/bitops.h>
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/ioport.h>
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#include <linux/interrupt.h>
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#include <asm/io.h>
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#include <asm/i8259.h>
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#include <asm/vr41xx/cmbvr4133.h>
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extern int vr4133_rockhopper;
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static int i8259_get_irq_number(int irq)
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{
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return i8259_irq();
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}
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void __init rockhopper_init_irq(void)
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{
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int i;
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if(!vr4133_rockhopper) {
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printk(KERN_ERR "Not a Rockhopper Board \n");
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return;
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}
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vr41xx_set_irq_trigger(CMBVR41XX_INTC_PIN, TRIGGER_LEVEL, SIGNAL_THROUGH);
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vr41xx_set_irq_level(CMBVR41XX_INTC_PIN, LEVEL_HIGH);
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vr41xx_cascade_irq(CMBVR41XX_INTC_IRQ, i8259_get_irq_number);
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}
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@ -1,249 +0,0 @@
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/*
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* arch/mips/vr41xx/nec-cmbvr4133/m1535plus.c
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*
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* Initialize for ALi M1535+(included M5229 and M5237).
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*
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* Author: Yoichi Yuasa <yyuasa@mvista.com, or source@mvista.com> and
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* Alex Sapkov <asapkov@ru.mvista.com>
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*
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* 2003-2004 (c) MontaVista, Software, Inc. This file is licensed under
|
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* the terms of the GNU General Public License version 2. This program
|
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* is licensed "as is" without any warranty of any kind, whether express
|
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* or implied.
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*
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* Support for NEC-CMBVR4133 in 2.6
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* Author: Manish Lachwani (mlachwani@mvista.com)
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*/
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/serial.h>
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#include <asm/vr41xx/cmbvr4133.h>
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#include <linux/pci.h>
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#include <asm/io.h>
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#define CONFIG_PORT(port) ((port) ? 0x3f0 : 0x370)
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#define DATA_PORT(port) ((port) ? 0x3f1 : 0x371)
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#define INDEX_PORT(port) CONFIG_PORT(port)
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#define ENTER_CONFIG_MODE(port) \
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do { \
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outb_p(0x51, CONFIG_PORT(port)); \
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outb_p(0x23, CONFIG_PORT(port)); \
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} while(0)
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#define SELECT_LOGICAL_DEVICE(port, dev_no) \
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do { \
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outb_p(0x07, INDEX_PORT(port)); \
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outb_p((dev_no), DATA_PORT(port)); \
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} while(0)
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#define WRITE_CONFIG_DATA(port, index, data) \
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do { \
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outb_p((index), INDEX_PORT(port)); \
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outb_p((data), DATA_PORT(port)); \
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} while(0)
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#define EXIT_CONFIG_MODE(port) outb(0xbb, CONFIG_PORT(port))
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#define PCI_CONFIG_ADDR KSEG1ADDR(0x0f000c18)
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#define PCI_CONFIG_DATA KSEG1ADDR(0x0f000c14)
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#ifdef CONFIG_BLK_DEV_FD
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void __devinit ali_m1535plus_fdc_init(int port)
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{
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||||
ENTER_CONFIG_MODE(port);
|
||||
SELECT_LOGICAL_DEVICE(port, 0); /* FDC */
|
||||
WRITE_CONFIG_DATA(port, 0x30, 0x01); /* FDC: enable */
|
||||
WRITE_CONFIG_DATA(port, 0x60, 0x03); /* I/O port base: 0x3f0 */
|
||||
WRITE_CONFIG_DATA(port, 0x61, 0xf0);
|
||||
WRITE_CONFIG_DATA(port, 0x70, 0x06); /* IRQ: 6 */
|
||||
WRITE_CONFIG_DATA(port, 0x74, 0x02); /* DMA: channel 2 */
|
||||
WRITE_CONFIG_DATA(port, 0xf0, 0x08);
|
||||
WRITE_CONFIG_DATA(port, 0xf1, 0x00);
|
||||
WRITE_CONFIG_DATA(port, 0xf2, 0xff);
|
||||
WRITE_CONFIG_DATA(port, 0xf4, 0x00);
|
||||
EXIT_CONFIG_MODE(port);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
void __devinit ali_m1535plus_parport_init(int port)
|
||||
{
|
||||
ENTER_CONFIG_MODE(port);
|
||||
SELECT_LOGICAL_DEVICE(port, 3); /* Parallel Port */
|
||||
WRITE_CONFIG_DATA(port, 0x30, 0x01);
|
||||
WRITE_CONFIG_DATA(port, 0x60, 0x03); /* I/O port base: 0x378 */
|
||||
WRITE_CONFIG_DATA(port, 0x61, 0x78);
|
||||
WRITE_CONFIG_DATA(port, 0x70, 0x07); /* IRQ: 7 */
|
||||
WRITE_CONFIG_DATA(port, 0x74, 0x04); /* DMA: None */
|
||||
WRITE_CONFIG_DATA(port, 0xf0, 0x8c); /* IRQ polarity: Active Low */
|
||||
WRITE_CONFIG_DATA(port, 0xf1, 0xc5);
|
||||
EXIT_CONFIG_MODE(port);
|
||||
}
|
||||
|
||||
void __devinit ali_m1535plus_keyboard_init(int port)
|
||||
{
|
||||
ENTER_CONFIG_MODE(port);
|
||||
SELECT_LOGICAL_DEVICE(port, 7); /* KEYBOARD */
|
||||
WRITE_CONFIG_DATA(port, 0x30, 0x01); /* KEYBOARD: eable */
|
||||
WRITE_CONFIG_DATA(port, 0x70, 0x01); /* IRQ: 1 */
|
||||
WRITE_CONFIG_DATA(port, 0x72, 0x0c); /* PS/2 Mouse IRQ: 12 */
|
||||
WRITE_CONFIG_DATA(port, 0xf0, 0x00);
|
||||
EXIT_CONFIG_MODE(port);
|
||||
}
|
||||
|
||||
void __devinit ali_m1535plus_hotkey_init(int port)
|
||||
{
|
||||
ENTER_CONFIG_MODE(port);
|
||||
SELECT_LOGICAL_DEVICE(port, 0xc); /* HOTKEY */
|
||||
WRITE_CONFIG_DATA(port, 0x30, 0x00);
|
||||
WRITE_CONFIG_DATA(port, 0xf0, 0x35);
|
||||
WRITE_CONFIG_DATA(port, 0xf1, 0x14);
|
||||
WRITE_CONFIG_DATA(port, 0xf2, 0x11);
|
||||
WRITE_CONFIG_DATA(port, 0xf3, 0x71);
|
||||
WRITE_CONFIG_DATA(port, 0xf5, 0x05);
|
||||
EXIT_CONFIG_MODE(port);
|
||||
}
|
||||
|
||||
void ali_m1535plus_init(struct pci_dev *dev)
|
||||
{
|
||||
pci_write_config_byte(dev, 0x40, 0x18); /* PCI Interface Control */
|
||||
pci_write_config_byte(dev, 0x41, 0xc0); /* PS2 keyb & mouse enable */
|
||||
pci_write_config_byte(dev, 0x42, 0x41); /* ISA bus cycle control */
|
||||
pci_write_config_byte(dev, 0x43, 0x00); /* ISA bus cycle control 2 */
|
||||
pci_write_config_byte(dev, 0x44, 0x5d); /* IDE enable & IRQ 14 */
|
||||
pci_write_config_byte(dev, 0x45, 0x0b); /* PCI int polling mode */
|
||||
pci_write_config_byte(dev, 0x47, 0x00); /* BIOS chip select control */
|
||||
|
||||
/* IRQ routing */
|
||||
pci_write_config_byte(dev, 0x48, 0x03); /* INTA IRQ10, INTB disable */
|
||||
pci_write_config_byte(dev, 0x49, 0x00); /* INTC and INTD disable */
|
||||
pci_write_config_byte(dev, 0x4a, 0x00); /* INTE and INTF disable */
|
||||
pci_write_config_byte(dev, 0x4b, 0x90); /* Audio IRQ11, Modem disable */
|
||||
|
||||
pci_write_config_word(dev, 0x50, 0x4000); /* Parity check IDE enable */
|
||||
pci_write_config_word(dev, 0x52, 0x0000); /* USB & RTC disable */
|
||||
pci_write_config_word(dev, 0x54, 0x0002); /* ??? no info */
|
||||
pci_write_config_word(dev, 0x56, 0x0002); /* PCS1J signal disable */
|
||||
|
||||
pci_write_config_byte(dev, 0x59, 0x00); /* PCSDS */
|
||||
pci_write_config_byte(dev, 0x5a, 0x00);
|
||||
pci_write_config_byte(dev, 0x5b, 0x00);
|
||||
pci_write_config_word(dev, 0x5c, 0x0000);
|
||||
pci_write_config_byte(dev, 0x5e, 0x00);
|
||||
pci_write_config_byte(dev, 0x5f, 0x00);
|
||||
pci_write_config_word(dev, 0x60, 0x0000);
|
||||
|
||||
pci_write_config_byte(dev, 0x6c, 0x00);
|
||||
pci_write_config_byte(dev, 0x6d, 0x48); /* ROM address mapping */
|
||||
pci_write_config_byte(dev, 0x6e, 0x00); /* ??? what for? */
|
||||
|
||||
pci_write_config_byte(dev, 0x70, 0x12); /* Serial IRQ control */
|
||||
pci_write_config_byte(dev, 0x71, 0xEF); /* DMA channel select */
|
||||
pci_write_config_byte(dev, 0x72, 0x03); /* USB IDSEL */
|
||||
pci_write_config_byte(dev, 0x73, 0x00); /* ??? no info */
|
||||
|
||||
/*
|
||||
* IRQ setup ALi M5237 USB Host Controller
|
||||
* IRQ: 9
|
||||
*/
|
||||
pci_write_config_byte(dev, 0x74, 0x01); /* USB IRQ9 */
|
||||
|
||||
pci_write_config_byte(dev, 0x75, 0x1f); /* IDE2 IRQ 15 */
|
||||
pci_write_config_byte(dev, 0x76, 0x80); /* ACPI disable */
|
||||
pci_write_config_byte(dev, 0x77, 0x40); /* Modem disable */
|
||||
pci_write_config_dword(dev, 0x78, 0x20000000); /* Pin select 2 */
|
||||
pci_write_config_byte(dev, 0x7c, 0x00); /* Pin select 3 */
|
||||
pci_write_config_byte(dev, 0x81, 0x00); /* ID read/write control */
|
||||
pci_write_config_byte(dev, 0x90, 0x00); /* PCI PM block control */
|
||||
pci_write_config_word(dev, 0xa4, 0x0000); /* PMSCR */
|
||||
|
||||
#ifdef CONFIG_BLK_DEV_FD
|
||||
ali_m1535plus_fdc_init(1);
|
||||
#endif
|
||||
|
||||
ali_m1535plus_keyboard_init(1);
|
||||
ali_m1535plus_hotkey_init(1);
|
||||
}
|
||||
|
||||
static inline void ali_config_writeb(u8 reg, u8 val, int devfn)
|
||||
{
|
||||
u32 data;
|
||||
int shift;
|
||||
|
||||
writel((1 << 16) | (devfn << 8) | (reg & 0xfc) | 1UL, PCI_CONFIG_ADDR);
|
||||
data = readl(PCI_CONFIG_DATA);
|
||||
|
||||
shift = (reg & 3) << 3;
|
||||
data &= ~(0xff << shift);
|
||||
data |= (((u32)val) << shift);
|
||||
|
||||
writel(data, PCI_CONFIG_DATA);
|
||||
}
|
||||
|
||||
static inline u8 ali_config_readb(u8 reg, int devfn)
|
||||
{
|
||||
u32 data;
|
||||
|
||||
writel((1 << 16) | (devfn << 8) | (reg & 0xfc) | 1UL, PCI_CONFIG_ADDR);
|
||||
data = readl(PCI_CONFIG_DATA);
|
||||
|
||||
return (u8)(data >> ((reg & 3) << 3));
|
||||
}
|
||||
|
||||
static inline u16 ali_config_readw(u8 reg, int devfn)
|
||||
{
|
||||
u32 data;
|
||||
|
||||
writel((1 << 16) | (devfn << 8) | (reg & 0xfc) | 1UL, PCI_CONFIG_ADDR);
|
||||
data = readl(PCI_CONFIG_DATA);
|
||||
|
||||
return (u16)(data >> ((reg & 2) << 3));
|
||||
}
|
||||
|
||||
int vr4133_rockhopper = 0;
|
||||
void __init ali_m5229_preinit(void)
|
||||
{
|
||||
if (ali_config_readw(PCI_VENDOR_ID, 16) == PCI_VENDOR_ID_AL &&
|
||||
ali_config_readw(PCI_DEVICE_ID, 16) == PCI_DEVICE_ID_AL_M1533) {
|
||||
printk(KERN_INFO "Found an NEC Rockhopper \n");
|
||||
vr4133_rockhopper = 1;
|
||||
/*
|
||||
* Enable ALi M5229 IDE Controller (both channels)
|
||||
* IDSEL: A27
|
||||
*/
|
||||
ali_config_writeb(0x58, 0x4c, 16);
|
||||
}
|
||||
}
|
||||
|
||||
void __init ali_m5229_init(struct pci_dev *dev)
|
||||
{
|
||||
/*
|
||||
* Enable Primary/Secondary Channel Cable Detect 40-Pin
|
||||
*/
|
||||
pci_write_config_word(dev, 0x4a, 0xc023);
|
||||
|
||||
/*
|
||||
* Set only the 3rd byteis for the master IDE's cycle and
|
||||
* enable Internal IDE Function
|
||||
*/
|
||||
pci_write_config_byte(dev, 0x50, 0x23); /* Class code attr register */
|
||||
|
||||
pci_write_config_byte(dev, 0x09, 0xff); /* Set native mode & stuff */
|
||||
pci_write_config_byte(dev, 0x52, 0x00); /* use timing registers */
|
||||
pci_write_config_byte(dev, 0x58, 0x02); /* Primary addr setup timing */
|
||||
pci_write_config_byte(dev, 0x59, 0x22); /* Primary cmd block timing */
|
||||
pci_write_config_byte(dev, 0x5a, 0x22); /* Pr drv 0 R/W timing */
|
||||
pci_write_config_byte(dev, 0x5b, 0x22); /* Pr drv 1 R/W timing */
|
||||
pci_write_config_byte(dev, 0x5c, 0x02); /* Sec addr setup timing */
|
||||
pci_write_config_byte(dev, 0x5d, 0x22); /* Sec cmd block timing */
|
||||
pci_write_config_byte(dev, 0x5e, 0x22); /* Sec drv 0 R/W timing */
|
||||
pci_write_config_byte(dev, 0x5f, 0x22); /* Sec drv 1 R/W timing */
|
||||
pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x20);
|
||||
pci_write_config_word(dev, PCI_COMMAND,
|
||||
PCI_COMMAND_PARITY | PCI_COMMAND_MASTER |
|
||||
PCI_COMMAND_IO);
|
||||
}
|
||||
|
||||
|
|
@ -1,89 +0,0 @@
|
|||
/*
|
||||
* arch/mips/vr41xx/nec-cmbvr4133/setup.c
|
||||
*
|
||||
* Setup for the NEC CMB-VR4133.
|
||||
*
|
||||
* Author: Yoichi Yuasa <yyuasa@mvista.com, or source@mvista.com> and
|
||||
* Alex Sapkov <asapkov@ru.mvista.com>
|
||||
*
|
||||
* 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under
|
||||
* the terms of the GNU General Public License version 2. This program
|
||||
* is licensed "as is" without any warranty of any kind, whether express
|
||||
* or implied.
|
||||
*
|
||||
* Support for CMBVR4133 board in 2.6
|
||||
* Author: Manish Lachwani (mlachwani@mvista.com)
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/ide.h>
|
||||
#include <linux/ioport.h>
|
||||
|
||||
#include <asm/reboot.h>
|
||||
#include <asm/time.h>
|
||||
#include <asm/vr41xx/cmbvr4133.h>
|
||||
#include <asm/bootinfo.h>
|
||||
|
||||
#ifdef CONFIG_MTD
|
||||
#include <linux/mtd/physmap.h>
|
||||
#include <linux/mtd/partitions.h>
|
||||
#include <linux/mtd/mtd.h>
|
||||
#include <linux/mtd/map.h>
|
||||
|
||||
static struct mtd_partition cmbvr4133_mtd_parts[] = {
|
||||
{
|
||||
.name = "User FS",
|
||||
.size = 0x1be0000,
|
||||
.offset = 0,
|
||||
.mask_flags = 0,
|
||||
},
|
||||
{
|
||||
.name = "PMON",
|
||||
.size = 0x140000,
|
||||
.offset = MTDPART_OFS_APPEND,
|
||||
.mask_flags = MTD_WRITEABLE, /* force read-only */
|
||||
},
|
||||
{
|
||||
.name = "User FS2",
|
||||
.size = MTDPART_SIZ_FULL,
|
||||
.offset = MTDPART_OFS_APPEND,
|
||||
.mask_flags = 0,
|
||||
}
|
||||
};
|
||||
|
||||
#define number_partitions ARRAY_SIZE(cmbvr4133_mtd_parts)
|
||||
#endif
|
||||
|
||||
extern void i8259_init(void);
|
||||
|
||||
static void __init nec_cmbvr4133_setup(void)
|
||||
{
|
||||
#ifdef CONFIG_ROCKHOPPER
|
||||
extern void disable_pcnet(void);
|
||||
|
||||
disable_pcnet();
|
||||
#endif
|
||||
set_io_port_base(KSEG1ADDR(0x16000000));
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
#ifdef CONFIG_ROCKHOPPER
|
||||
ali_m5229_preinit();
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ROCKHOPPER
|
||||
rockhopper_init_irq();
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MTD
|
||||
/* we use generic physmap mapping driver and we use partitions */
|
||||
physmap_configure(0x1C000000, 0x02000000, 4, NULL);
|
||||
physmap_set_partitions(cmbvr4133_mtd_parts, number_partitions);
|
||||
#endif
|
||||
|
||||
/* 128 MB memory support */
|
||||
add_memory_region(0, 0x08000000, BOOT_MEM_RAM);
|
||||
|
||||
#ifdef CONFIG_ROCKHOPPER
|
||||
i8259_init();
|
||||
#endif
|
||||
}
|
||||
|
|
@ -2,9 +2,6 @@
|
|||
#define __ASM_MACH_VR41XX_IRQ_H
|
||||
|
||||
#include <asm/vr41xx/irq.h> /* for MIPS_CPU_IRQ_BASE */
|
||||
#ifdef CONFIG_NEC_CMBVR4133
|
||||
#include <asm/vr41xx/cmbvr4133.h> /* for I8259A_IRQ_BASE */
|
||||
#endif
|
||||
|
||||
#include_next <irq.h>
|
||||
|
||||
|
|
|
|||
|
|
@ -1,56 +0,0 @@
|
|||
/*
|
||||
* include/asm-mips/vr41xx/cmbvr4133.h
|
||||
*
|
||||
* Include file for NEC CMB-VR4133.
|
||||
*
|
||||
* Author: Yoichi Yuasa <yyuasa@mvista.com, or source@mvista.com> and
|
||||
* Jun Sun <jsun@mvista.com, or source@mvista.com> and
|
||||
* Alex Sapkov <asapkov@ru.mvista.com>
|
||||
*
|
||||
* 2002-2004 (c) MontaVista, Software, Inc. This file is licensed under
|
||||
* the terms of the GNU General Public License version 2. This program
|
||||
* is licensed "as is" without any warranty of any kind, whether express
|
||||
* or implied.
|
||||
*/
|
||||
#ifndef __NEC_CMBVR4133_H
|
||||
#define __NEC_CMBVR4133_H
|
||||
|
||||
#include <asm/vr41xx/irq.h>
|
||||
|
||||
/*
|
||||
* General-Purpose I/O Pin Number
|
||||
*/
|
||||
#define CMBVR41XX_INTA_PIN 1
|
||||
#define CMBVR41XX_INTB_PIN 1
|
||||
#define CMBVR41XX_INTC_PIN 3
|
||||
#define CMBVR41XX_INTD_PIN 1
|
||||
#define CMBVR41XX_INTE_PIN 1
|
||||
|
||||
/*
|
||||
* Interrupt Number
|
||||
*/
|
||||
#define CMBVR41XX_INTA_IRQ GIU_IRQ(CMBVR41XX_INTA_PIN)
|
||||
#define CMBVR41XX_INTB_IRQ GIU_IRQ(CMBVR41XX_INTB_PIN)
|
||||
#define CMBVR41XX_INTC_IRQ GIU_IRQ(CMBVR41XX_INTC_PIN)
|
||||
#define CMBVR41XX_INTD_IRQ GIU_IRQ(CMBVR41XX_INTD_PIN)
|
||||
#define CMBVR41XX_INTE_IRQ GIU_IRQ(CMBVR41XX_INTE_PIN)
|
||||
|
||||
#define I8259A_IRQ_BASE 72
|
||||
#define I8259_IRQ(x) (I8259A_IRQ_BASE + (x))
|
||||
#define TIMER_IRQ I8259_IRQ(0)
|
||||
#define KEYBOARD_IRQ I8259_IRQ(1)
|
||||
#define I8259_SLAVE_IRQ I8259_IRQ(2)
|
||||
#define UART3_IRQ I8259_IRQ(3)
|
||||
#define UART1_IRQ I8259_IRQ(4)
|
||||
#define UART2_IRQ I8259_IRQ(5)
|
||||
#define FDC_IRQ I8259_IRQ(6)
|
||||
#define PARPORT_IRQ I8259_IRQ(7)
|
||||
#define RTC_IRQ I8259_IRQ(8)
|
||||
#define USB_IRQ I8259_IRQ(9)
|
||||
#define I8259_INTA_IRQ I8259_IRQ(10)
|
||||
#define AUDIO_IRQ I8259_IRQ(11)
|
||||
#define AUX_IRQ I8259_IRQ(12)
|
||||
#define IDE_PRIMARY_IRQ I8259_IRQ(14)
|
||||
#define IDE_SECONDARY_IRQ I8259_IRQ(15)
|
||||
|
||||
#endif /* __NEC_CMBVR4133_H */
|
||||
Loading…
Reference in a new issue