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drm/nouveau/ltc/gm107: wait on relevant bit in gm107_ltc_cbc_wait

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Patch "ltc/gm107: use nvkm_mask to set cbc_ctrl1" sets the 3rd bit
of the CTRL1 register instead of writing it entirely in
gm107_ltc_cbc_clear(). As a counterpart, gm107_ltc_cbc_wait() must also
be modified to wait on that single bit only, otherwise a timeout may
occur if some other bit of that register is set. This happened at least
on GM206 when running glmark2-drm.

While we are at it, use the more compact nvkm_wait_msec() to wait for
the bit to clear.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Alexandre Courbot 2016-01-15 11:53:24 +09:00 committed by Ben Skeggs
parent 67d1c0a25c
commit f0db6e3be9
1 changed files with 2 additions and 4 deletions
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6
drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm107.c
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@ -43,10 +43,8 @@ gm107_ltc_cbc_wait(struct nvkm_ltc *ltc)
for (c = 0; c < ltc->ltc_nr; c++) { for (c = 0; c < ltc->ltc_nr; c++) {
for (s = 0; s < ltc->lts_nr; s++) { for (s = 0; s < ltc->lts_nr; s++) {
const u32 addr = 0x14046c + (c * 0x2000) + (s * 0x200); const u32 addr = 0x14046c + (c * 0x2000) + (s * 0x200);
nvkm_msec(device, 2000, nvkm_wait_msec(device, 2000, addr,
if (!nvkm_rd32(device, addr)) 0x00000004, 0x00000000);
break;
);
} }
} }
} }