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Device tree changes for omap variants for SDHCI

Browse source 
This series adds the devicetree configuration needed for pinctrl on
 dra7 variants to use the SDHCI SDIO driver instead of mmc-omap-hs
 driver. To use SDHCI, both the pins and the iodelay needs to be
 configured.
 
 This series is based on the related SDHCI drivers changes on a branch
 set up by Ulf.
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Merge tag 'omap-for-v4.18/dt-sdhci-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/dt

Device tree changes for omap variants for SDHCI

This series adds the devicetree configuration needed for pinctrl on
dra7 variants to use the SDHCI SDIO driver instead of mmc-omap-hs
driver. To use SDHCI, both the pins and the iodelay needs to be
configured.

This series is based on the related SDHCI drivers changes on a branch
set up by Ulf.

* tag 'omap-for-v4.18/dt-sdhci-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (28 commits)
  Documentation: ARM: Add new MMC requirements for DRA7/K2G
  ARM: dts: dra7: Add high speed modes capability to MMC1/MMC2 dt node
  ARM: dts: dra7: Use sdhci-omap programming model
  ARM: dts: dra76-evm: Add wilink8 wlan support
  ARM: dts: dra7-evm: Add wilink8 wlan support
  ARM: dts: dra7-evm: Model EVM_3V6 regulator
  ARM: dts: dra72-evm-common: Add wilink8 wlan support
  ARM: dts: am57xx-beagle-x15/am57xx-idk: Fix pinctrl-names
  ARM: dts: am574x-idk: Add pinmux configuration for MMC
  ARM: dts: dra71-evm: Use pinctrl group from dra7-mmc-iodelay.dtsi to select pulldown
  ARM: dts: am57xx-idk: Use pinctrl group from dra7-mmc-iodelay.dtsi to select pulldown
  ARM: dts: dra7-mmc-iodelay: Add a new pinctrl group for clk line without pullup
  ARM: dts: dra71-evm: Add "vqmmc-supply" property for mmc2
  ARM: dts: dra72-evm-common: Remove mmc specific pinmux
  mmc: sdhci-omap: Get IODelay values for 3.3v DDR mode
  dt-bindings: sdhci-omap: Add pinctrl bindings
  mmc: sdhci-omap: Add sdhci_omap specific ops for enable_sdio_irq
  mmc: sdhci-omap: Add support for MMC/SD controller in k2g SoC
  dt-bindings: sdhci-omap: Add K2G specific binding
  mmc: sdhci-omap: Workaround for Errata i834
  ...

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2018-05-14 09:19:45 -07:00
commit f4f8ef04a1
20 changed files with 469 additions and 119 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
Documentation/arm/OMAP/README
View file

@ -5,3 +5,7 @@ KERNEL NEW DEPENDENCIES
v4.3+ Update is needed for custom .config files to make sure v4.3+ Update is needed for custom .config files to make sure
CONFIG_REGULATOR_PBIAS is enabled for MMC1 to work CONFIG_REGULATOR_PBIAS is enabled for MMC1 to work
properly. properly.
v4.18+ Update is needed for custom .config files to make sure
CONFIG_MMC_SDHCI_OMAP is enabled for all MMC instances
to work in DRA7 and K2G based boards.

7
Documentation/devicetree/bindings/mmc/sdhci-omap.txt
View file

@ -4,7 +4,14 @@ Refer to mmc.txt for standard MMC bindings.
Required properties: Required properties:
- compatible: Should be "ti,dra7-sdhci" for DRA7 and DRA72 controllers - compatible: Should be "ti,dra7-sdhci" for DRA7 and DRA72 controllers
Should be "ti,k2g-sdhci" for K2G
- ti,hwmods: Must be "mmc<n>", <n> is controller instance starting 1 - ti,hwmods: Must be "mmc<n>", <n> is controller instance starting 1
(Not required for K2G).
- pinctrl-names: Should be subset of "default", "hs", "sdr12", "sdr25", "sdr50",
"ddr50-rev11", "sdr104-rev11", "ddr50", "sdr104",
"ddr_1_8v-rev11", "ddr_1_8v" or "ddr_3_3v", "hs200_1_8v-rev11",
"hs200_1_8v",
- pinctrl-<n> : Pinctrl states as described in bindings/pinctrl/pinctrl-bindings.txt
Example: Example:
mmc1: mmc@4809c000 { mmc1: mmc@4809c000 {

5
arch/arm/boot/dts/am571x-idk.dts
View file

@ -10,6 +10,7 @@
#include "dra72x.dtsi" #include "dra72x.dtsi"
#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/irq.h>
#include "dra7-mmc-iodelay.dtsi"
#include "dra72x-mmc-iodelay.dtsi" #include "dra72x-mmc-iodelay.dtsi"
#include "am57xx-idk-common.dtsi" #include "am57xx-idk-common.dtsi"
@ -102,7 +103,7 @@
&mmc1 { &mmc1 {
pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104"; pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
pinctrl-0 = <&mmc1_pins_default>; pinctrl-0 = <&mmc1_pins_default_no_clk_pu>;
pinctrl-1 = <&mmc1_pins_hs>; pinctrl-1 = <&mmc1_pins_hs>;
pinctrl-2 = <&mmc1_pins_sdr12>; pinctrl-2 = <&mmc1_pins_sdr12>;
pinctrl-3 = <&mmc1_pins_sdr25>; pinctrl-3 = <&mmc1_pins_sdr25>;
@ -112,7 +113,7 @@
}; };
&mmc2 { &mmc2 {
pinctrl-names = "default", "hs", "ddr_1_8v"; pinctrl-names = "default", "hs", "ddr_3_3v";
pinctrl-0 = <&mmc2_pins_default>; pinctrl-0 = <&mmc2_pins_default>;
pinctrl-1 = <&mmc2_pins_hs>; pinctrl-1 = <&mmc2_pins_hs>;
pinctrl-2 = <&mmc2_pins_ddr_rev20 &mmc2_iodelay_ddr_conf>; pinctrl-2 = <&mmc2_pins_ddr_rev20 &mmc2_iodelay_ddr_conf>;

5
arch/arm/boot/dts/am572x-idk.dts
View file

@ -9,6 +9,7 @@
/dts-v1/; /dts-v1/;
#include "dra74x.dtsi" #include "dra74x.dtsi"
#include "dra7-mmc-iodelay.dtsi"
#include "dra74x-mmc-iodelay.dtsi" #include "dra74x-mmc-iodelay.dtsi"
#include "am572x-idk-common.dtsi" #include "am572x-idk-common.dtsi"
@ -20,7 +21,7 @@
&mmc1 { &mmc1 {
pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104"; pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
pinctrl-0 = <&mmc1_pins_default>; pinctrl-0 = <&mmc1_pins_default_no_clk_pu>;
pinctrl-1 = <&mmc1_pins_hs>; pinctrl-1 = <&mmc1_pins_hs>;
pinctrl-2 = <&mmc1_pins_sdr12>; pinctrl-2 = <&mmc1_pins_sdr12>;
pinctrl-3 = <&mmc1_pins_sdr25>; pinctrl-3 = <&mmc1_pins_sdr25>;
@ -30,7 +31,7 @@
}; };
&mmc2 { &mmc2 {
pinctrl-names = "default", "hs", "ddr_1_8v"; pinctrl-names = "default", "hs", "ddr_3_3v";
pinctrl-0 = <&mmc2_pins_default>; pinctrl-0 = <&mmc2_pins_default>;
pinctrl-1 = <&mmc2_pins_hs>; pinctrl-1 = <&mmc2_pins_hs>;
pinctrl-2 = <&mmc2_pins_ddr_rev20>; pinctrl-2 = <&mmc2_pins_ddr_rev20>;

20
arch/arm/boot/dts/am574x-idk.dts
View file

@ -7,6 +7,8 @@
/dts-v1/; /dts-v1/;
#include "dra76x.dtsi" #include "dra76x.dtsi"
#include "dra7-mmc-iodelay.dtsi"
#include "dra76x-mmc-iodelay.dtsi"
#include "am572x-idk-common.dtsi" #include "am572x-idk-common.dtsi"
/ { / {
@ -20,3 +22,21 @@
spi-max-frequency = <96000000>; spi-max-frequency = <96000000>;
}; };
}; };
&mmc1 {
pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
pinctrl-0 = <&mmc1_pins_default_no_clk_pu>;
pinctrl-1 = <&mmc1_pins_hs>;
pinctrl-2 = <&mmc1_pins_default>;
pinctrl-3 = <&mmc1_pins_hs>;
pinctrl-4 = <&mmc1_pins_sdr50>;
pinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_conf>;
pinctrl-6 = <&mmc1_pins_ddr50 &mmc1_iodelay_sdr104_conf>;
};
&mmc2 {
pinctrl-names = "default", "hs", "ddr_3_3v";
pinctrl-0 = <&mmc2_pins_default>;
pinctrl-1 = <&mmc2_pins_default>;
pinctrl-2 = <&mmc2_pins_default>;
};

4
arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi
View file

@ -444,8 +444,8 @@
vmmc-supply = <&vdd_3v3>; vmmc-supply = <&vdd_3v3>;
vqmmc-supply = <&vdd_3v3>; vqmmc-supply = <&vdd_3v3>;
bus-width = <8>; bus-width = <8>;
ti,non-removable; non-removable;
cap-mmc-dual-data-rate; no-1-8-v;
}; };
&sata { &sata {

3
arch/arm/boot/dts/am57xx-beagle-x15.dts
View file

@ -25,10 +25,11 @@
pinctrl-1 = <&mmc1_pins_hs>; pinctrl-1 = <&mmc1_pins_hs>;
vmmc-supply = <&ldo1_reg>; vmmc-supply = <&ldo1_reg>;
no-1-8-v;
}; };
&mmc2 { &mmc2 {
pinctrl-names = "default", "hs", "ddr_1_8v"; pinctrl-names = "default", "hs", "ddr_3_3v";
pinctrl-0 = <&mmc2_pins_default>; pinctrl-0 = <&mmc2_pins_default>;
pinctrl-1 = <&mmc2_pins_hs>; pinctrl-1 = <&mmc2_pins_hs>;
pinctrl-2 = <&mmc2_pins_ddr_3_3v_rev11 &mmc2_iodelay_ddr_3_3v_rev11_conf>; pinctrl-2 = <&mmc2_pins_ddr_3_3v_rev11 &mmc2_iodelay_ddr_3_3v_rev11_conf>;

14
arch/arm/boot/dts/am57xx-idk-common.dtsi
View file

@ -115,17 +115,6 @@
DRA7XX_CORE_IOPAD(0x37d4, MUX_MODE15 | PULL_UP) /* dcan1_rx.off */ DRA7XX_CORE_IOPAD(0x37d4, MUX_MODE15 | PULL_UP) /* dcan1_rx.off */
>; >;
}; };
mmc1_pins_default: mmc1_pins_default {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mmc1_clk.clk */
DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
>;
};
}; };
&i2c1 { &i2c1 {
@ -423,8 +412,9 @@
vmmc-supply = <&v3_3d>; vmmc-supply = <&v3_3d>;
vqmmc-supply = <&v3_3d>; vqmmc-supply = <&v3_3d>;
bus-width = <8>; bus-width = <8>;
ti,non-removable; non-removable;
max-frequency = <96000000>; max-frequency = <96000000>;
no-1-8-v;
}; };
&dcan1 { &dcan1 {

15
arch/arm/boot/dts/dra7-evm-common.dtsi
View file

@ -260,3 +260,18 @@
&pcie1_rc { &pcie1_rc {
status = "okay"; status = "okay";
}; };
&mmc4 {
bus-width = <4>;
cap-power-off-card;
keep-power-in-suspend;
non-removable;
#address-cells = <1>;
#size-cells = <0>;
wifi@2 {
compatible = "ti,wl1835";
reg = <2>;
interrupt-parent = <&gpio5>;
interrupts = <7 IRQ_TYPE_EDGE_RISING>;
};
};

68
arch/arm/boot/dts/dra7-evm.dts
View file

@ -20,6 +20,16 @@
reg = <0x0 0x80000000 0x0 0x60000000>; /* 1536 MB */ reg = <0x0 0x80000000 0x0 0x60000000>; /* 1536 MB */
}; };
evm_12v0: fixedregulator-evm_12v0 {
/* main supply */
compatible = "regulator-fixed";
regulator-name = "evm_12v0";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
regulator-always-on;
regulator-boot-on;
};
evm_1v8_sw: fixedregulator-evm_1v8 { evm_1v8_sw: fixedregulator-evm_1v8 {
compatible = "regulator-fixed"; compatible = "regulator-fixed";
regulator-name = "evm_1v8"; regulator-name = "evm_1v8";
@ -54,6 +64,48 @@
regulator-max-microvolt = <1800000>; regulator-max-microvolt = <1800000>;
}; };
evm_3v3: fixedregulator-evm3v3 {
/* Output of Cntlr A of TPS43351-Q1 on dra7-evm */
compatible = "regulator-fixed";
regulator-name = "evm_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&evm_12v0>;
regulator-always-on;
regulator-boot-on;
};
evm_5v0: fixedregulator-evm_5v0 {
/* Output of Cntlr B of TPS43351-Q1 on dra7-evm */
compatible = "regulator-fixed";
regulator-name = "evm_5v0";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&evm_12v0>;
regulator-always-on;
regulator-boot-on;
};
evm_3v6: fixedregulator-evm_3v6 {
compatible = "regulator-fixed";
regulator-name = "evm_3v6";
regulator-min-microvolt = <3600000>;
regulator-max-microvolt = <3600000>;
vin-supply = <&evm_5v0>;
regulator-always-on;
regulator-boot-on;
};
vmmcwl_fixed: fixedregulator-mmcwl {
compatible = "regulator-fixed";
regulator-name = "vmmcwl_fixed";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
gpio = <&gpio5 8 0>;
startup-delay-us = <70000>;
enable-active-high;
};
extcon_usb2: extcon_usb2 { extcon_usb2: extcon_usb2 {
compatible = "linux,extcon-usb-gpio"; compatible = "linux,extcon-usb-gpio";
id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>; id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
@ -325,6 +377,7 @@
vmmc-supply = <&evm_1v8_sw>; vmmc-supply = <&evm_1v8_sw>;
vqmmc-supply = <&evm_1v8_sw>; vqmmc-supply = <&evm_1v8_sw>;
bus-width = <8>; bus-width = <8>;
non-removable;
pinctrl-names = "default", "hs", "ddr_1_8v-rev11", "ddr_1_8v", "hs200_1_8v-rev11", "hs200_1_8v"; pinctrl-names = "default", "hs", "ddr_1_8v-rev11", "ddr_1_8v", "hs200_1_8v-rev11", "hs200_1_8v";
pinctrl-0 = <&mmc2_pins_default>; pinctrl-0 = <&mmc2_pins_default>;
pinctrl-1 = <&mmc2_pins_hs>; pinctrl-1 = <&mmc2_pins_hs>;
@ -334,6 +387,21 @@
pinctrl-5 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev20_conf>; pinctrl-5 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev20_conf>;
}; };
&mmc4 {
status = "okay";
vmmc-supply = <&evm_3v6>;
vqmmc-supply = <&vmmcwl_fixed>;
pinctrl-names = "default-rev11", "default", "hs-rev11", "hs", "sdr12-rev11", "sdr12", "sdr25-rev11", "sdr25";
pinctrl-0 = <&mmc4_pins_default &mmc4_iodelay_ds_rev11_conf>;
pinctrl-1 = <&mmc4_pins_default &mmc4_iodelay_ds_rev20_conf>;
pinctrl-2 = <&mmc4_pins_hs &mmc4_iodelay_sdr12_hs_sdr25_rev11_conf>;
pinctrl-3 = <&mmc4_pins_hs &mmc4_iodelay_sdr12_hs_sdr25_rev20_conf>;
pinctrl-4 = <&mmc4_pins_sdr12 &mmc4_iodelay_sdr12_hs_sdr25_rev11_conf>;
pinctrl-5 = <&mmc4_pins_sdr12 &mmc4_iodelay_sdr12_hs_sdr25_rev20_conf>;
pinctrl-6 = <&mmc4_pins_sdr25 &mmc4_iodelay_sdr12_hs_sdr25_rev11_conf>;
pinctrl-7 = <&mmc4_pins_sdr25 &mmc4_iodelay_sdr12_hs_sdr25_rev20_conf>;
};
&cpu0 { &cpu0 {
vdd-supply = <&smps123_reg>; vdd-supply = <&smps123_reg>;
}; };

19
arch/arm/boot/dts/dra7-mmc-iodelay.dtsi Normal file
View file

@ -0,0 +1,19 @@
// SPDX-License-Identifier: GPL-2.0
/*
* MMC IOdelay values for TI's DRA7xx SoCs.
* Copyright (C) 2018 Texas Instruments
* Author: Kishon Vijay Abraham I <kishon@ti.com>
*/
&dra7_pmx_core {
mmc1_pins_default_no_clk_pu: mmc1_pins_default_no_clk_pu {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mmc1_clk.clk */
DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
>;
};
};

32
arch/arm/boot/dts/dra7.dtsi
View file

@ -1079,17 +1079,15 @@
}; };
mmc1: mmc@4809c000 { mmc1: mmc@4809c000 {
compatible = "ti,omap4-hsmmc"; compatible = "ti,dra7-sdhci";
reg = <0x4809c000 0x400>; reg = <0x4809c000 0x400>;
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmc1"; ti,hwmods = "mmc1";
ti,dual-volt;
ti,needs-special-reset;
dmas = <&sdma_xbar 61>, <&sdma_xbar 62>;
dma-names = "tx", "rx";
status = "disabled"; status = "disabled";
pbias-supply = <&pbias_mmc_reg>; pbias-supply = <&pbias_mmc_reg>;
max-frequency = <192000000>; max-frequency = <192000000>;
mmc-ddr-1_8v;
mmc-ddr-3_3v;
}; };
hdqw1w: 1w@480b2000 { hdqw1w: 1w@480b2000 {
@ -1100,40 +1098,40 @@
}; };
mmc2: mmc@480b4000 { mmc2: mmc@480b4000 {
compatible = "ti,omap4-hsmmc"; compatible = "ti,dra7-sdhci";
reg = <0x480b4000 0x400>; reg = <0x480b4000 0x400>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmc2"; ti,hwmods = "mmc2";
ti,needs-special-reset;
dmas = <&sdma_xbar 47>, <&sdma_xbar 48>;
dma-names = "tx", "rx";
status = "disabled"; status = "disabled";
max-frequency = <192000000>; max-frequency = <192000000>;
/* SDR104/DDR50/SDR50 bits in CAPA2 is not supported */
sdhci-caps-mask = <0x7 0x0>;
mmc-hs200-1_8v;
mmc-ddr-1_8v;
mmc-ddr-3_3v;
}; };
mmc3: mmc@480ad000 { mmc3: mmc@480ad000 {
compatible = "ti,omap4-hsmmc"; compatible = "ti,dra7-sdhci";
reg = <0x480ad000 0x400>; reg = <0x480ad000 0x400>;
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmc3"; ti,hwmods = "mmc3";
ti,needs-special-reset;
dmas = <&sdma_xbar 77>, <&sdma_xbar 78>;
dma-names = "tx", "rx";
status = "disabled"; status = "disabled";
/* Errata i887 limits max-frequency of MMC3 to 64 MHz */ /* Errata i887 limits max-frequency of MMC3 to 64 MHz */
max-frequency = <64000000>; max-frequency = <64000000>;
/* SDMA is not supported */
sdhci-caps-mask = <0x0 0x400000>;
}; };
mmc4: mmc@480d1000 { mmc4: mmc@480d1000 {
compatible = "ti,omap4-hsmmc"; compatible = "ti,dra7-sdhci";
reg = <0x480d1000 0x400>; reg = <0x480d1000 0x400>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmc4"; ti,hwmods = "mmc4";
ti,needs-special-reset;
dmas = <&sdma_xbar 57>, <&sdma_xbar 58>;
dma-names = "tx", "rx";
status = "disabled"; status = "disabled";
max-frequency = <192000000>; max-frequency = <192000000>;
/* SDMA is not supported */
sdhci-caps-mask = <0x0 0x400000>;
}; };
mmu0_dsp1: mmu@40d01000 { mmu0_dsp1: mmu@40d01000 {

17
arch/arm/boot/dts/dra71-evm.dts
View file

@ -7,6 +7,7 @@
*/ */
#include "dra72-evm-common.dtsi" #include "dra72-evm-common.dtsi"
#include "dra7-mmc-iodelay.dtsi"
#include "dra72x-mmc-iodelay.dtsi" #include "dra72x-mmc-iodelay.dtsi"
#include <dt-bindings/net/ti-dp83867.h> #include <dt-bindings/net/ti-dp83867.h>
@ -50,19 +51,6 @@
}; };
}; };
&dra7_pmx_core {
mmc1_pins_default: mmc1_pins_default {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mmc1_clk.clk */
DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
>;
};
};
&i2c1 { &i2c1 {
status = "okay"; status = "okay";
clock-frequency = <400000>; clock-frequency = <400000>;
@ -187,7 +175,7 @@
&mmc1 { &mmc1 {
pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104"; pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
pinctrl-0 = <&mmc1_pins_default>; pinctrl-0 = <&mmc1_pins_default_no_clk_pu>;
pinctrl-1 = <&mmc1_pins_hs>; pinctrl-1 = <&mmc1_pins_hs>;
pinctrl-2 = <&mmc1_pins_sdr12>; pinctrl-2 = <&mmc1_pins_sdr12>;
pinctrl-3 = <&mmc1_pins_sdr25>; pinctrl-3 = <&mmc1_pins_sdr25>;
@ -204,6 +192,7 @@
pinctrl-2 = <&mmc2_pins_ddr_rev20 &mmc2_iodelay_ddr_conf>; pinctrl-2 = <&mmc2_pins_ddr_rev20 &mmc2_iodelay_ddr_conf>;
pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev20_conf>; pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev20_conf>;
vmmc-supply = <&evm_1v8_sw>; vmmc-supply = <&evm_1v8_sw>;
vqmmc-supply = <&evm_1v8_sw>;
}; };
&mac { &mac {

71
arch/arm/boot/dts/dra72-evm-common.dtsi
View file

@ -44,6 +44,16 @@
regulator-boot-on; regulator-boot-on;
}; };
evm_3v6: fixedregulator-evm_3v6 {
compatible = "regulator-fixed";
regulator-name = "evm_3v6";
regulator-min-microvolt = <3600000>;
regulator-max-microvolt = <3600000>;
vin-supply = <&evm_5v0>;
regulator-always-on;
regulator-boot-on;
};
vsys_3v3: fixedregulator-vsys3v3 { vsys_3v3: fixedregulator-vsys3v3 {
/* Output 2 of TPS43351QDAPRQ1 on dra72-evm */ /* Output 2 of TPS43351QDAPRQ1 on dra72-evm */
/* Output 2 of LM5140QRWGTQ1 on dra71-evm */ /* Output 2 of LM5140QRWGTQ1 on dra71-evm */
@ -171,36 +181,18 @@
clocks = <&atl_clkin2_ck>; clocks = <&atl_clkin2_ck>;
}; };
}; };
vmmcwl_fixed: fixedregulator-mmcwl {
compatible = "regulator-fixed";
regulator-name = "vmmcwl_fixed";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
gpio = <&gpio5 8 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
}; };
&dra7_pmx_core { &dra7_pmx_core {
mmc1_pins_default: mmc1_pins_default {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */
DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
>;
};
mmc2_pins_default: mmc2_pins_default {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
>;
};
dcan1_pins_default: dcan1_pins_default { dcan1_pins_default: dcan1_pins_default {
pinctrl-single,pins = < pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */ DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
@ -421,10 +413,33 @@
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&mmc2_pins_default>; pinctrl-0 = <&mmc2_pins_default>;
bus-width = <8>; bus-width = <8>;
ti,non-removable; non-removable;
max-frequency = <192000000>; max-frequency = <192000000>;
}; };
&mmc4 {
status = "okay";
vmmc-supply = <&evm_3v6>;
vqmmc-supply = <&vmmcwl_fixed>;
bus-width = <4>;
cap-power-off-card;
keep-power-in-suspend;
non-removable;
pinctrl-names = "default", "hs", "sdr12", "sdr25";
pinctrl-0 = <&mmc4_pins_default>;
pinctrl-1 = <&mmc4_pins_default>;
pinctrl-2 = <&mmc4_pins_default>;
pinctrl-3 = <&mmc4_pins_default>;
#address-cells = <1>;
#size-cells = <0>;
wifi@2 {
compatible = "ti,wl1835";
reg = <2>;
interrupt-parent = <&gpio5>;
interrupts = <7 IRQ_TYPE_EDGE_RISING>;
};
};
&mac { &mac {
status = "okay"; status = "okay";
}; };

11
arch/arm/boot/dts/dra72x-mmc-iodelay.dtsi
View file

@ -202,6 +202,17 @@
DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
>; >;
}; };
mmc4_pins_default: mmc4_pins_default {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
>;
};
}; };
&dra7_iodelay_core { &dra7_iodelay_core {

34
arch/arm/boot/dts/dra76-evm.dts
View file

@ -42,6 +42,16 @@
regulator-boot-on; regulator-boot-on;
}; };
vio_3v6: fixedregulator-vio_3v6 {
compatible = "regulator-fixed";
regulator-name = "vio_3v6";
regulator-min-microvolt = <3600000>;
regulator-max-microvolt = <3600000>;
vin-supply = <&vsys_5v0>;
regulator-always-on;
regulator-boot-on;
};
vsys_3v3: fixedregulator-vsys3v3 { vsys_3v3: fixedregulator-vsys3v3 {
/* Output of Cntlr A of TPS43351-Q1 on dra76-evm */ /* Output of Cntlr A of TPS43351-Q1 on dra76-evm */
compatible = "regulator-fixed"; compatible = "regulator-fixed";
@ -81,6 +91,16 @@
vin-supply = <&smps5_reg>; vin-supply = <&smps5_reg>;
}; };
vmmcwl_fixed: fixedregulator-mmcwl {
compatible = "regulator-fixed";
regulator-name = "vmmcwl_fixed";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
gpio = <&gpio5 8 0>; /* gpio5_8 */
startup-delay-us = <70000>;
enable-active-high;
};
vtt_fixed: fixedregulator-vtt { vtt_fixed: fixedregulator-vtt {
compatible = "regulator-fixed"; compatible = "regulator-fixed";
regulator-name = "vtt_fixed"; regulator-name = "vtt_fixed";
@ -307,7 +327,7 @@
&mmc1 { &mmc1 {
status = "okay"; status = "okay";
vmmc-supply = <&vio_3v3_sd>; vmmc-supply = <&vio_3v3_sd>;
vmmc_aux-supply = <&ldo4_reg>; vqmmc-supply = <&ldo4_reg>;
bus-width = <4>; bus-width = <4>;
/* /*
* SDCD signal is not being used here - using the fact that GPIO mode * SDCD signal is not being used here - using the fact that GPIO mode
@ -324,6 +344,7 @@
vmmc-supply = <&vio_1v8>; vmmc-supply = <&vio_1v8>;
vqmmc-supply = <&vio_1v8>; vqmmc-supply = <&vio_1v8>;
bus-width = <8>; bus-width = <8>;
non-removable;
pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v"; pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v";
pinctrl-0 = <&mmc2_pins_default>; pinctrl-0 = <&mmc2_pins_default>;
pinctrl-1 = <&mmc2_pins_default>; pinctrl-1 = <&mmc2_pins_default>;
@ -331,6 +352,17 @@
pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_conf>; pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_conf>;
}; };
&mmc4 {
status = "okay";
vmmc-supply = <&vio_3v6>;
vqmmc-supply = <&vmmcwl_fixed>;
pinctrl-names = "default", "hs", "sdr12", "sdr25";
pinctrl-0 = <&mmc4_pins_hs &mmc4_iodelay_default_conf>;
pinctrl-1 = <&mmc4_pins_hs &mmc4_iodelay_manual1_conf>;
pinctrl-2 = <&mmc4_pins_hs &mmc4_iodelay_manual1_conf>;
pinctrl-3 = <&mmc4_pins_hs &mmc4_iodelay_manual1_conf>;
};
/* No RTC on this device */ /* No RTC on this device */
&rtc { &rtc {
status = "disabled"; status = "disabled";

88
drivers/mmc/host/sdhci-omap.c
View file

@ -26,6 +26,7 @@
#include <linux/pm_runtime.h> #include <linux/pm_runtime.h>
#include <linux/regulator/consumer.h> #include <linux/regulator/consumer.h>
#include <linux/pinctrl/consumer.h> #include <linux/pinctrl/consumer.h>
#include <linux/sys_soc.h>
#include "sdhci-pltfm.h" #include "sdhci-pltfm.h"
@ -35,6 +36,7 @@
#define CON_DDR BIT(19) #define CON_DDR BIT(19)
#define CON_CLKEXTFREE BIT(16) #define CON_CLKEXTFREE BIT(16)
#define CON_PADEN BIT(15) #define CON_PADEN BIT(15)
#define CON_CTPL BIT(11)
#define CON_INIT BIT(1) #define CON_INIT BIT(1)
#define CON_OD BIT(0) #define CON_OD BIT(0)
@ -100,6 +102,7 @@ struct sdhci_omap_data {
}; };
struct sdhci_omap_host { struct sdhci_omap_host {
char *version;
void __iomem *base; void __iomem *base;
struct device *dev; struct device *dev;
struct regulator *pbias; struct regulator *pbias;
@ -224,6 +227,23 @@ static void sdhci_omap_conf_bus_power(struct sdhci_omap_host *omap_host,
} }
} }
static void sdhci_omap_enable_sdio_irq(struct mmc_host *mmc, int enable)
{
struct sdhci_host *host = mmc_priv(mmc);
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
u32 reg;
reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
if (enable)
reg |= (CON_CTPL | CON_CLKEXTFREE);
else
reg &= ~(CON_CTPL | CON_CLKEXTFREE);
sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
sdhci_enable_sdio_irq(mmc, enable);
}
static inline void sdhci_omap_set_dll(struct sdhci_omap_host *omap_host, static inline void sdhci_omap_set_dll(struct sdhci_omap_host *omap_host,
int count) int count)
{ {
@ -713,10 +733,15 @@ static const struct sdhci_pltfm_data sdhci_omap_pdata = {
SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC, SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC,
.quirks2 = SDHCI_QUIRK2_ACMD23_BROKEN | .quirks2 = SDHCI_QUIRK2_ACMD23_BROKEN |
SDHCI_QUIRK2_PRESET_VALUE_BROKEN | SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
SDHCI_QUIRK2_RSP_136_HAS_CRC, SDHCI_QUIRK2_RSP_136_HAS_CRC |
SDHCI_QUIRK2_DISABLE_HW_TIMEOUT,
.ops = &sdhci_omap_ops, .ops = &sdhci_omap_ops,
}; };
static const struct sdhci_omap_data k2g_data = {
.offset = 0x200,
};
static const struct sdhci_omap_data dra7_data = { static const struct sdhci_omap_data dra7_data = {
.offset = 0x200, .offset = 0x200,
.flags = SDHCI_OMAP_REQUIRE_IODELAY, .flags = SDHCI_OMAP_REQUIRE_IODELAY,
@ -724,6 +749,7 @@ static const struct sdhci_omap_data dra7_data = {
static const struct of_device_id omap_sdhci_match[] = { static const struct of_device_id omap_sdhci_match[] = {
{ .compatible = "ti,dra7-sdhci", .data = &dra7_data }, { .compatible = "ti,dra7-sdhci", .data = &dra7_data },
{ .compatible = "ti,k2g-sdhci", .data = &k2g_data },
{}, {},
}; };
MODULE_DEVICE_TABLE(of, omap_sdhci_match); MODULE_DEVICE_TABLE(of, omap_sdhci_match);
@ -733,12 +759,21 @@ static struct pinctrl_state
u32 *caps, u32 capmask) u32 *caps, u32 capmask)
{ {
struct device *dev = omap_host->dev; struct device *dev = omap_host->dev;
char *version = omap_host->version;
struct pinctrl_state *pinctrl_state = ERR_PTR(-ENODEV); struct pinctrl_state *pinctrl_state = ERR_PTR(-ENODEV);
char str[20];
if (!(*caps & capmask)) if (!(*caps & capmask))
goto ret; goto ret;
if (version) {
snprintf(str, 20, "%s-%s", mode, version);
pinctrl_state = pinctrl_lookup_state(omap_host->pinctrl, str);
}
if (IS_ERR(pinctrl_state))
pinctrl_state = pinctrl_lookup_state(omap_host->pinctrl, mode); pinctrl_state = pinctrl_lookup_state(omap_host->pinctrl, mode);
if (IS_ERR(pinctrl_state)) { if (IS_ERR(pinctrl_state)) {
dev_err(dev, "no pinctrl state for %s mode", mode); dev_err(dev, "no pinctrl state for %s mode", mode);
*caps &= ~capmask; *caps &= ~capmask;
@ -807,8 +842,15 @@ static int sdhci_omap_config_iodelay_pinctrl_state(struct sdhci_omap_host
state = sdhci_omap_iodelay_pinctrl_state(omap_host, "ddr_1_8v", caps, state = sdhci_omap_iodelay_pinctrl_state(omap_host, "ddr_1_8v", caps,
MMC_CAP_1_8V_DDR); MMC_CAP_1_8V_DDR);
if (!IS_ERR(state)) {
pinctrl_state[MMC_TIMING_MMC_DDR52] = state;
} else {
state = sdhci_omap_iodelay_pinctrl_state(omap_host, "ddr_3_3v",
caps,
MMC_CAP_3_3V_DDR);
if (!IS_ERR(state)) if (!IS_ERR(state))
pinctrl_state[MMC_TIMING_MMC_DDR52] = state; pinctrl_state[MMC_TIMING_MMC_DDR52] = state;
}
state = sdhci_omap_iodelay_pinctrl_state(omap_host, "hs", caps, state = sdhci_omap_iodelay_pinctrl_state(omap_host, "hs", caps,
MMC_CAP_SD_HIGHSPEED); MMC_CAP_SD_HIGHSPEED);
@ -830,6 +872,16 @@ static int sdhci_omap_config_iodelay_pinctrl_state(struct sdhci_omap_host
return 0; return 0;
} }
static const struct soc_device_attribute sdhci_omap_soc_devices[] = {
{
.machine = "DRA7[45]*",
.revision = "ES1.[01]",
},
{
/* sentinel */
}
};
static int sdhci_omap_probe(struct platform_device *pdev) static int sdhci_omap_probe(struct platform_device *pdev)
{ {
int ret; int ret;
@ -841,6 +893,7 @@ static int sdhci_omap_probe(struct platform_device *pdev)
struct mmc_host *mmc; struct mmc_host *mmc;
const struct of_device_id *match; const struct of_device_id *match;
struct sdhci_omap_data *data; struct sdhci_omap_data *data;
const struct soc_device_attribute *soc;
match = of_match_device(omap_sdhci_match, dev); match = of_match_device(omap_sdhci_match, dev);
if (!match) if (!match)
@ -871,10 +924,22 @@ static int sdhci_omap_probe(struct platform_device *pdev)
host->ioaddr += offset; host->ioaddr += offset;
mmc = host->mmc; mmc = host->mmc;
sdhci_get_of_property(pdev);
ret = mmc_of_parse(mmc); ret = mmc_of_parse(mmc);
if (ret) if (ret)
goto err_pltfm_free; goto err_pltfm_free;
soc = soc_device_match(sdhci_omap_soc_devices);
if (soc) {
omap_host->version = "rev11";
if (!strcmp(dev_name(dev), "4809c000.mmc"))
mmc->f_max = 96000000;
if (!strcmp(dev_name(dev), "480b4000.mmc"))
mmc->f_max = 48000000;
if (!strcmp(dev_name(dev), "480ad000.mmc"))
mmc->f_max = 48000000;
}
pltfm_host->clk = devm_clk_get(dev, "fck"); pltfm_host->clk = devm_clk_get(dev, "fck");
if (IS_ERR(pltfm_host->clk)) { if (IS_ERR(pltfm_host->clk)) {
ret = PTR_ERR(pltfm_host->clk); ret = PTR_ERR(pltfm_host->clk);
@ -916,26 +981,31 @@ static int sdhci_omap_probe(struct platform_device *pdev)
goto err_put_sync; goto err_put_sync;
} }
ret = sdhci_omap_config_iodelay_pinctrl_state(omap_host);
if (ret)
goto err_put_sync;
host->mmc_host_ops.get_ro = mmc_gpio_get_ro; host->mmc_host_ops.get_ro = mmc_gpio_get_ro;
host->mmc_host_ops.start_signal_voltage_switch = host->mmc_host_ops.start_signal_voltage_switch =
sdhci_omap_start_signal_voltage_switch; sdhci_omap_start_signal_voltage_switch;
host->mmc_host_ops.set_ios = sdhci_omap_set_ios; host->mmc_host_ops.set_ios = sdhci_omap_set_ios;
host->mmc_host_ops.card_busy = sdhci_omap_card_busy; host->mmc_host_ops.card_busy = sdhci_omap_card_busy;
host->mmc_host_ops.execute_tuning = sdhci_omap_execute_tuning; host->mmc_host_ops.execute_tuning = sdhci_omap_execute_tuning;
host->mmc_host_ops.enable_sdio_irq = sdhci_omap_enable_sdio_irq;
sdhci_read_caps(host); ret = sdhci_setup_host(host);
host->caps |= SDHCI_CAN_DO_ADMA2;
ret = sdhci_add_host(host);
if (ret) if (ret)
goto err_put_sync; goto err_put_sync;
ret = sdhci_omap_config_iodelay_pinctrl_state(omap_host);
if (ret)
goto err_cleanup_host;
ret = __sdhci_add_host(host);
if (ret)
goto err_cleanup_host;
return 0; return 0;
err_cleanup_host:
sdhci_cleanup_host(host);
err_put_sync: err_put_sync:
pm_runtime_put_sync(dev); pm_runtime_put_sync(dev);

144
drivers/mmc/host/sdhci.c
View file

@ -709,29 +709,16 @@ static u32 sdhci_sdma_address(struct sdhci_host *host)
return sg_dma_address(host->data->sg); return sg_dma_address(host->data->sg);
} }
static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd) static unsigned int sdhci_target_timeout(struct sdhci_host *host,
struct mmc_command *cmd,
struct mmc_data *data)
{ {
u8 count; unsigned int target_timeout;
struct mmc_data *data = cmd->data;
unsigned target_timeout, current_timeout;
/*
* If the host controller provides us with an incorrect timeout
* value, just skip the check and use 0xE. The hardware may take
* longer to time out, but that's much better than having a too-short
* timeout value.
*/
if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
return 0xE;
/* Unspecified timeout, assume max */
if (!data && !cmd->busy_timeout)
return 0xE;
/* timeout in us */ /* timeout in us */
if (!data) if (!data) {
target_timeout = cmd->busy_timeout * 1000; target_timeout = cmd->busy_timeout * 1000;
else { } else {
target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000); target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000);
if (host->clock && data->timeout_clks) { if (host->clock && data->timeout_clks) {
unsigned long long val; unsigned long long val;
@ -748,6 +735,67 @@ static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
} }
} }
return target_timeout;
}
static void sdhci_calc_sw_timeout(struct sdhci_host *host,
struct mmc_command *cmd)
{
struct mmc_data *data = cmd->data;
struct mmc_host *mmc = host->mmc;
struct mmc_ios *ios = &mmc->ios;
unsigned char bus_width = 1 << ios->bus_width;
unsigned int blksz;
unsigned int freq;
u64 target_timeout;
u64 transfer_time;
target_timeout = sdhci_target_timeout(host, cmd, data);
target_timeout *= NSEC_PER_USEC;
if (data) {
blksz = data->blksz;
freq = host->mmc->actual_clock ? : host->clock;
transfer_time = (u64)blksz * NSEC_PER_SEC * (8 / bus_width);
do_div(transfer_time, freq);
/* multiply by '2' to account for any unknowns */
transfer_time = transfer_time * 2;
/* calculate timeout for the entire data */
host->data_timeout = data->blocks * target_timeout +
transfer_time;
} else {
host->data_timeout = target_timeout;
}
if (host->data_timeout)
host->data_timeout += MMC_CMD_TRANSFER_TIME;
}
static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd,
bool *too_big)
{
u8 count;
struct mmc_data *data = cmd->data;
unsigned target_timeout, current_timeout;
*too_big = true;
/*
* If the host controller provides us with an incorrect timeout
* value, just skip the check and use 0xE. The hardware may take
* longer to time out, but that's much better than having a too-short
* timeout value.
*/
if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
return 0xE;
/* Unspecified timeout, assume max */
if (!data && !cmd->busy_timeout)
return 0xE;
/* timeout in us */
target_timeout = sdhci_target_timeout(host, cmd, data);
/* /*
* Figure out needed cycles. * Figure out needed cycles.
* We do this in steps in order to fit inside a 32 bit int. * We do this in steps in order to fit inside a 32 bit int.
@ -768,9 +816,12 @@ static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
} }
if (count >= 0xF) { if (count >= 0xF) {
if (!(host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT))
DBG("Too large timeout 0x%x requested for CMD%d!\n", DBG("Too large timeout 0x%x requested for CMD%d!\n",
count, cmd->opcode); count, cmd->opcode);
count = 0xE; count = 0xE;
} else {
*too_big = false;
} }
return count; return count;
@ -790,6 +841,16 @@ static void sdhci_set_transfer_irqs(struct sdhci_host *host)
sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
} }
static void sdhci_set_data_timeout_irq(struct sdhci_host *host, bool enable)
{
if (enable)
host->ier |= SDHCI_INT_DATA_TIMEOUT;
else
host->ier &= ~SDHCI_INT_DATA_TIMEOUT;
sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
}
static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
{ {
u8 count; u8 count;
@ -797,7 +858,18 @@ static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
if (host->ops->set_timeout) { if (host->ops->set_timeout) {
host->ops->set_timeout(host, cmd); host->ops->set_timeout(host, cmd);
} else { } else {
count = sdhci_calc_timeout(host, cmd); bool too_big = false;
count = sdhci_calc_timeout(host, cmd, &too_big);
if (too_big &&
host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT) {
sdhci_calc_sw_timeout(host, cmd);
sdhci_set_data_timeout_irq(host, false);
} else if (!(host->ier & SDHCI_INT_DATA_TIMEOUT)) {
sdhci_set_data_timeout_irq(host, true);
}
sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL); sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
} }
} }
@ -807,6 +879,8 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
u8 ctrl; u8 ctrl;
struct mmc_data *data = cmd->data; struct mmc_data *data = cmd->data;
host->data_timeout = 0;
if (sdhci_data_line_cmd(cmd)) if (sdhci_data_line_cmd(cmd))
sdhci_set_timeout(host, cmd); sdhci_set_timeout(host, cmd);
@ -1160,13 +1234,6 @@ void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
mdelay(1); mdelay(1);
} }
timeout = jiffies;
if (!cmd->data && cmd->busy_timeout > 9000)
timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
else
timeout += 10 * HZ;
sdhci_mod_timer(host, cmd->mrq, timeout);
host->cmd = cmd; host->cmd = cmd;
if (sdhci_data_line_cmd(cmd)) { if (sdhci_data_line_cmd(cmd)) {
WARN_ON(host->data_cmd); WARN_ON(host->data_cmd);
@ -1206,6 +1273,15 @@ void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200) cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
flags |= SDHCI_CMD_DATA; flags |= SDHCI_CMD_DATA;
timeout = jiffies;
if (host->data_timeout)
timeout += nsecs_to_jiffies(host->data_timeout);
else if (!cmd->data && cmd->busy_timeout > 9000)
timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
else
timeout += 10 * HZ;
sdhci_mod_timer(host, cmd->mrq, timeout);
sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND); sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
} }
EXPORT_SYMBOL_GPL(sdhci_send_command); EXPORT_SYMBOL_GPL(sdhci_send_command);
@ -3616,6 +3692,10 @@ int sdhci_setup_host(struct sdhci_host *host)
mmc->max_busy_timeout /= host->timeout_clk; mmc->max_busy_timeout /= host->timeout_clk;
} }
if (host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT &&
!host->ops->get_max_timeout_count)
mmc->max_busy_timeout = 0;
mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23; mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
@ -3672,6 +3752,16 @@ int sdhci_setup_host(struct sdhci_host *host)
if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) { if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) {
host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
SDHCI_SUPPORT_DDR50); SDHCI_SUPPORT_DDR50);
/*
* The SDHCI controller in a SoC might support HS200/HS400
* (indicated using mmc-hs200-1_8v/mmc-hs400-1_8v dt property),
* but if the board is modeled such that the IO lines are not
* connected to 1.8v then HS200/HS400 cannot be supported.
* Disable HS200/HS400 if the board does not have 1.8v connected
* to the IO lines. (Applicable for other modes in 1.8v)
*/
mmc->caps2 &= ~(MMC_CAP2_HSX00_1_8V | MMC_CAP2_HS400_ES);
mmc->caps &= ~(MMC_CAP_1_8V_DDR | MMC_CAP_UHS);
} }
/* Any UHS-I mode in caps implies SDR12 and SDR25 support. */ /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */

15
drivers/mmc/host/sdhci.h
View file

@ -332,6 +332,14 @@ struct sdhci_adma2_64_desc {
/* Allow for a a command request and a data request at the same time */ /* Allow for a a command request and a data request at the same time */
#define SDHCI_MAX_MRQS 2 #define SDHCI_MAX_MRQS 2
/*
* 48bit command and 136 bit response in 100KHz clock could take upto 2.48ms.
* However since the start time of the command, the time between
* command and response, and the time between response and start of data is
* not known, set the command transfer time to 10ms.
*/
#define MMC_CMD_TRANSFER_TIME (10 * NSEC_PER_MSEC) /* max 10 ms */
enum sdhci_cookie { enum sdhci_cookie {
COOKIE_UNMAPPED, COOKIE_UNMAPPED,
COOKIE_PRE_MAPPED, /* mapped by sdhci_pre_req() */ COOKIE_PRE_MAPPED, /* mapped by sdhci_pre_req() */
@ -437,6 +445,11 @@ struct sdhci_host {
#define SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN (1<<15) #define SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN (1<<15)
/* Controller has CRC in 136 bit Command Response */ /* Controller has CRC in 136 bit Command Response */
#define SDHCI_QUIRK2_RSP_136_HAS_CRC (1<<16) #define SDHCI_QUIRK2_RSP_136_HAS_CRC (1<<16)
/*
* Disable HW timeout if the requested timeout is more than the maximum
* obtainable timeout.
*/
#define SDHCI_QUIRK2_DISABLE_HW_TIMEOUT (1<<17)
int irq; /* Device IRQ */ int irq; /* Device IRQ */
void __iomem *ioaddr; /* Mapped address */ void __iomem *ioaddr; /* Mapped address */
@ -550,6 +563,8 @@ struct sdhci_host {
/* Host SDMA buffer boundary. */ /* Host SDMA buffer boundary. */
u32 sdma_boundary; u32 sdma_boundary;
u64 data_timeout;
unsigned long private[0] ____cacheline_aligned; unsigned long private[0] ____cacheline_aligned;
}; };

4
include/linux/mmc/host.h
View file

@ -320,6 +320,9 @@ struct mmc_host {
#define MMC_CAP_UHS_SDR50 (1 << 18) /* Host supports UHS SDR50 mode */ #define MMC_CAP_UHS_SDR50 (1 << 18) /* Host supports UHS SDR50 mode */
#define MMC_CAP_UHS_SDR104 (1 << 19) /* Host supports UHS SDR104 mode */ #define MMC_CAP_UHS_SDR104 (1 << 19) /* Host supports UHS SDR104 mode */
#define MMC_CAP_UHS_DDR50 (1 << 20) /* Host supports UHS DDR50 mode */ #define MMC_CAP_UHS_DDR50 (1 << 20) /* Host supports UHS DDR50 mode */
#define MMC_CAP_UHS (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | \
MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 | \
MMC_CAP_UHS_DDR50)
/* (1 << 21) is free for reuse */ /* (1 << 21) is free for reuse */
#define MMC_CAP_DRIVER_TYPE_A (1 << 23) /* Host supports Driver Type A */ #define MMC_CAP_DRIVER_TYPE_A (1 << 23) /* Host supports Driver Type A */
#define MMC_CAP_DRIVER_TYPE_C (1 << 24) /* Host supports Driver Type C */ #define MMC_CAP_DRIVER_TYPE_C (1 << 24) /* Host supports Driver Type C */
@ -345,6 +348,7 @@ struct mmc_host {
#define MMC_CAP2_HS400_1_2V (1 << 16) /* Can support HS400 1.2V */ #define MMC_CAP2_HS400_1_2V (1 << 16) /* Can support HS400 1.2V */
#define MMC_CAP2_HS400 (MMC_CAP2_HS400_1_8V | \ #define MMC_CAP2_HS400 (MMC_CAP2_HS400_1_8V | \
MMC_CAP2_HS400_1_2V) MMC_CAP2_HS400_1_2V)
#define MMC_CAP2_HSX00_1_8V (MMC_CAP2_HS200_1_8V_SDR | MMC_CAP2_HS400_1_8V)
#define MMC_CAP2_HSX00_1_2V (MMC_CAP2_HS200_1_2V_SDR | MMC_CAP2_HS400_1_2V) #define MMC_CAP2_HSX00_1_2V (MMC_CAP2_HS200_1_2V_SDR | MMC_CAP2_HS400_1_2V)
#define MMC_CAP2_SDIO_IRQ_NOTHREAD (1 << 17) #define MMC_CAP2_SDIO_IRQ_NOTHREAD (1 << 17)
#define MMC_CAP2_NO_WRITE_PROTECT (1 << 18) /* No physical write protect pin, assume that card is always read-write */ #define MMC_CAP2_NO_WRITE_PROTECT (1 << 18) /* No physical write protect pin, assume that card is always read-write */