drm/i915/gvt: Refine shadow batch buffer
1) Use standard i915 GEM object sequence to access the shadow batch buffer. 2) Manage i915 vma life cycle to solve one FIXME. v2: - Refine code structure. - Refine the usage of GEM APIs. - Add the missing lock/unlock in release_shadow_batch_buffer. Test on my SKL NuC. Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
This commit is contained in:
Zhi Wang
Zhenyu Wang
parent
58facf8c46
commit
f52c380a48
3 changed files with 101 additions and 72 deletions
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@ -1645,11 +1645,10 @@ static int find_bb_size(struct parser_exec_state *s, unsigned long *bb_size)
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static int perform_bb_shadow(struct parser_exec_state *s)
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{
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struct intel_shadow_bb_entry *entry_obj;
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struct intel_vgpu *vgpu = s->vgpu;
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struct intel_vgpu_shadow_bb *bb;
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unsigned long gma = 0;
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unsigned long bb_size;
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void *dst = NULL;
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int ret = 0;
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/* get the start gm address of the batch buffer */
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@ -1657,51 +1656,51 @@ static int perform_bb_shadow(struct parser_exec_state *s)
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if (gma == INTEL_GVT_INVALID_ADDR)
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return -EFAULT;
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/* get the size of the batch buffer */
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ret = find_bb_size(s, &bb_size);
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if (ret)
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return ret;
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/* allocate shadow batch buffer */
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entry_obj = kmalloc(sizeof(*entry_obj), GFP_KERNEL);
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if (entry_obj == NULL)
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bb = kzalloc(sizeof(*bb), GFP_KERNEL);
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if (!bb)
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return -ENOMEM;
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entry_obj->obj =
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i915_gem_object_create(s->vgpu->gvt->dev_priv,
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roundup(bb_size, PAGE_SIZE));
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if (IS_ERR(entry_obj->obj)) {
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ret = PTR_ERR(entry_obj->obj);
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goto free_entry;
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}
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entry_obj->len = bb_size;
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INIT_LIST_HEAD(&entry_obj->list);
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dst = i915_gem_object_pin_map(entry_obj->obj, I915_MAP_WB);
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if (IS_ERR(dst)) {
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ret = PTR_ERR(dst);
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goto put_obj;
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bb->obj = i915_gem_object_create(s->vgpu->gvt->dev_priv,
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roundup(bb_size, PAGE_SIZE));
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if (IS_ERR(bb->obj)) {
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ret = PTR_ERR(bb->obj);
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goto err_free_bb;
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}
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ret = i915_gem_object_set_to_cpu_domain(entry_obj->obj, false);
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if (ret) {
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gvt_vgpu_err("failed to set shadow batch to CPU\n");
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goto unmap_src;
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ret = i915_gem_obj_prepare_shmem_write(bb->obj, &bb->clflush);
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if (ret)
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goto err_free_obj;
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bb->va = i915_gem_object_pin_map(bb->obj, I915_MAP_WB);
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if (IS_ERR(bb->va)) {
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ret = PTR_ERR(bb->va);
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goto err_finish_shmem_access;
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}
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entry_obj->va = dst;
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entry_obj->bb_start_cmd_va = s->ip_va;
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if (bb->clflush & CLFLUSH_BEFORE) {
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drm_clflush_virt_range(bb->va, bb->obj->base.size);
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bb->clflush &= ~CLFLUSH_BEFORE;
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}
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/* copy batch buffer to shadow batch buffer*/
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ret = copy_gma_to_hva(s->vgpu, s->vgpu->gtt.ggtt_mm,
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gma, gma + bb_size,
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dst);
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bb->va);
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if (ret < 0) {
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gvt_vgpu_err("fail to copy guest ring buffer\n");
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goto unmap_src;
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ret = -EFAULT;
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goto err_unmap;
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}
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list_add(&entry_obj->list, &s->workload->shadow_bb);
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INIT_LIST_HEAD(&bb->list);
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list_add(&bb->list, &s->workload->shadow_bb);
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bb->accessing = true;
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bb->bb_start_cmd_va = s->ip_va;
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/*
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* ip_va saves the virtual address of the shadow batch buffer, while
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* ip_gma saves the graphics address of the original batch buffer.
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@ -1710,17 +1709,17 @@ static int perform_bb_shadow(struct parser_exec_state *s)
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* buffer's gma in pair. After all, we don't want to pin the shadow
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* buffer here (too early).
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*/
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s->ip_va = dst;
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s->ip_va = bb->va;
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s->ip_gma = gma;
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return 0;
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unmap_src:
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i915_gem_object_unpin_map(entry_obj->obj);
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put_obj:
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i915_gem_object_put(entry_obj->obj);
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free_entry:
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kfree(entry_obj);
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err_unmap:
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i915_gem_object_unpin_map(bb->obj);
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err_finish_shmem_access:
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i915_gem_obj_finish_shmem_access(bb->obj);
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err_free_obj:
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i915_gem_object_put(bb->obj);
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err_free_bb:
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kfree(bb);
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return ret;
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}
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@ -1762,7 +1761,6 @@ static int cmd_handler_mi_batch_buffer_start(struct parser_exec_state *s)
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if (ret < 0)
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return ret;
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}
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return ret;
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}
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@ -325,31 +325,46 @@ err_scan:
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return ret;
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}
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static void release_shadow_batch_buffer(struct intel_vgpu_workload *workload);
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static int prepare_shadow_batch_buffer(struct intel_vgpu_workload *workload)
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{
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struct intel_gvt *gvt = workload->vgpu->gvt;
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const int gmadr_bytes = gvt->device_info.gmadr_bytes_in_cmd;
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struct intel_shadow_bb_entry *entry_obj;
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struct intel_vgpu_shadow_bb *bb;
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int ret;
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/* pin the gem object to ggtt */
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list_for_each_entry(entry_obj, &workload->shadow_bb, list) {
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struct i915_vma *vma;
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list_for_each_entry(bb, &workload->shadow_bb, list) {
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bb->vma = i915_gem_object_ggtt_pin(bb->obj, NULL, 0, 0, 0);
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if (IS_ERR(bb->vma)) {
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ret = PTR_ERR(bb->vma);
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goto err;
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}
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vma = i915_gem_object_ggtt_pin(entry_obj->obj, NULL, 0, 4, 0);
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if (IS_ERR(vma))
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return PTR_ERR(vma);
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/* FIXME: we are not tracking our pinned VMA leaving it
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* up to the core to fix up the stray pin_count upon
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* free.
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*/
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/* update the relocate gma with shadow batch buffer*/
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entry_obj->bb_start_cmd_va[1] = i915_ggtt_offset(vma);
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/* relocate shadow batch buffer */
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bb->bb_start_cmd_va[1] = i915_ggtt_offset(bb->vma);
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if (gmadr_bytes == 8)
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entry_obj->bb_start_cmd_va[2] = 0;
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bb->bb_start_cmd_va[2] = 0;
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/* No one is going to touch shadow bb from now on. */
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if (bb->clflush & CLFLUSH_AFTER) {
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drm_clflush_virt_range(bb->va, bb->obj->base.size);
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bb->clflush &= ~CLFLUSH_AFTER;
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}
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ret = i915_gem_object_set_to_gtt_domain(bb->obj, false);
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if (ret)
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goto err;
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i915_gem_obj_finish_shmem_access(bb->obj);
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bb->accessing = false;
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i915_vma_move_to_active(bb->vma, workload->req, 0);
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}
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return 0;
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err:
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release_shadow_batch_buffer(workload);
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return ret;
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}
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static int update_wa_ctx_2_shadow_ctx(struct intel_shadow_wa_ctx *wa_ctx)
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@ -410,22 +425,37 @@ static int prepare_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
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static void release_shadow_batch_buffer(struct intel_vgpu_workload *workload)
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{
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/* release all the shadow batch buffer */
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if (!list_empty(&workload->shadow_bb)) {
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struct intel_shadow_bb_entry *entry_obj =
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list_first_entry(&workload->shadow_bb,
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struct intel_shadow_bb_entry,
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list);
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struct intel_shadow_bb_entry *temp;
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struct intel_vgpu *vgpu = workload->vgpu;
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struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
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struct intel_vgpu_shadow_bb *bb, *pos;
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list_for_each_entry_safe(entry_obj, temp, &workload->shadow_bb,
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list) {
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i915_gem_object_unpin_map(entry_obj->obj);
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i915_gem_object_put(entry_obj->obj);
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list_del(&entry_obj->list);
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kfree(entry_obj);
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if (list_empty(&workload->shadow_bb))
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return;
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bb = list_first_entry(&workload->shadow_bb,
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struct intel_vgpu_shadow_bb, list);
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mutex_lock(&dev_priv->drm.struct_mutex);
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list_for_each_entry_safe(bb, pos, &workload->shadow_bb, list) {
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if (bb->obj) {
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if (bb->accessing)
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i915_gem_obj_finish_shmem_access(bb->obj);
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if (bb->va && !IS_ERR(bb->va))
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i915_gem_object_unpin_map(bb->obj);
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if (bb->vma && !IS_ERR(bb->vma)) {
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i915_vma_unpin(bb->vma);
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i915_vma_close(bb->vma);
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}
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__i915_gem_object_release_unless_active(bb->obj);
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}
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list_del(&bb->list);
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kfree(bb);
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}
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mutex_unlock(&dev_priv->drm.struct_mutex);
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}
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static int prepare_workload(struct intel_vgpu_workload *workload)
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@ -112,13 +112,14 @@ struct intel_vgpu_workload {
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struct intel_shadow_wa_ctx wa_ctx;
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};
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/* Intel shadow batch buffer is a i915 gem object */
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struct intel_shadow_bb_entry {
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struct intel_vgpu_shadow_bb {
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struct list_head list;
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struct drm_i915_gem_object *obj;
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struct i915_vma *vma;
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void *va;
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unsigned long len;
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u32 *bb_start_cmd_va;
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unsigned int clflush;
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bool accessing;
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};
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#define workload_q_head(vgpu, ring_id) \
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