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pinctrl: sunxi: make use of raw_spinlock variants

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The sunxi pinctrl driver currently implement an irq_chip for handling
interrupts; due to how irq_chip handling is done, it's necessary for the
irq_chip methods to be invoked from hardirq context, even on a a
real-time kernel.  Because the spinlock_t type becomes a "sleeping"
spinlock w/ RT kernels, it is not suitable to be used with irq_chips.

A quick audit of the operations under the lock reveal that they do only
minimal, bounded work, and are therefore safe to do under a raw spinlock.

Signed-off-by: Julia Cartwright <julia@ni.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Julia Cartwright 2017-03-09 10:22:06 -06:00 committed by Linus Walleij
parent 82e529c1c7
commit f658ed3642
2 changed files with 14 additions and 14 deletions
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26
drivers/pinctrl/sunxi/pinctrl-sunxi.c
View file

@ -581,11 +581,11 @@ static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev,
return -ENOTSUPP; return -ENOTSUPP;
} }
spin_lock_irqsave(&pctl->lock, flags); raw_spin_lock_irqsave(&pctl->lock, flags);
reg = readl(pctl->membase + offset); reg = readl(pctl->membase + offset);
reg &= ~(mask << shift); reg &= ~(mask << shift);
writel(reg | val << shift, pctl->membase + offset); writel(reg | val << shift, pctl->membase + offset);
spin_unlock_irqrestore(&pctl->lock, flags); raw_spin_unlock_irqrestore(&pctl->lock, flags);
} /* for each config */ } /* for each config */
return 0; return 0;
@ -634,7 +634,7 @@ static void sunxi_pmx_set(struct pinctrl_dev *pctldev,
unsigned long flags; unsigned long flags;
u32 val, mask; u32 val, mask;
spin_lock_irqsave(&pctl->lock, flags); raw_spin_lock_irqsave(&pctl->lock, flags);
pin -= pctl->desc->pin_base; pin -= pctl->desc->pin_base;
val = readl(pctl->membase + sunxi_mux_reg(pin)); val = readl(pctl->membase + sunxi_mux_reg(pin));
@ -642,7 +642,7 @@ static void sunxi_pmx_set(struct pinctrl_dev *pctldev,
writel((val & ~mask) | config << sunxi_mux_offset(pin), writel((val & ~mask) | config << sunxi_mux_offset(pin),
pctl->membase + sunxi_mux_reg(pin)); pctl->membase + sunxi_mux_reg(pin));
spin_unlock_irqrestore(&pctl->lock, flags); raw_spin_unlock_irqrestore(&pctl->lock, flags);
} }
static int sunxi_pmx_set_mux(struct pinctrl_dev *pctldev, static int sunxi_pmx_set_mux(struct pinctrl_dev *pctldev,
@ -733,7 +733,7 @@ static void sunxi_pinctrl_gpio_set(struct gpio_chip *chip,
unsigned long flags; unsigned long flags;
u32 regval; u32 regval;
spin_lock_irqsave(&pctl->lock, flags); raw_spin_lock_irqsave(&pctl->lock, flags);
regval = readl(pctl->membase + reg); regval = readl(pctl->membase + reg);
@ -744,7 +744,7 @@ static void sunxi_pinctrl_gpio_set(struct gpio_chip *chip,
writel(regval, pctl->membase + reg); writel(regval, pctl->membase + reg);
spin_unlock_irqrestore(&pctl->lock, flags); raw_spin_unlock_irqrestore(&pctl->lock, flags);
} }
static int sunxi_pinctrl_gpio_direction_output(struct gpio_chip *chip, static int sunxi_pinctrl_gpio_direction_output(struct gpio_chip *chip,
@ -856,7 +856,7 @@ static int sunxi_pinctrl_irq_set_type(struct irq_data *d, unsigned int type)
return -EINVAL; return -EINVAL;
} }
spin_lock_irqsave(&pctl->lock, flags); raw_spin_lock_irqsave(&pctl->lock, flags);
if (type & IRQ_TYPE_LEVEL_MASK) if (type & IRQ_TYPE_LEVEL_MASK)
irq_set_chip_handler_name_locked(d, &sunxi_pinctrl_level_irq_chip, irq_set_chip_handler_name_locked(d, &sunxi_pinctrl_level_irq_chip,
@ -869,7 +869,7 @@ static int sunxi_pinctrl_irq_set_type(struct irq_data *d, unsigned int type)
regval &= ~(IRQ_CFG_IRQ_MASK << index); regval &= ~(IRQ_CFG_IRQ_MASK << index);
writel(regval | (mode << index), pctl->membase + reg); writel(regval | (mode << index), pctl->membase + reg);
spin_unlock_irqrestore(&pctl->lock, flags); raw_spin_unlock_irqrestore(&pctl->lock, flags);
return 0; return 0;
} }
@ -893,13 +893,13 @@ static void sunxi_pinctrl_irq_mask(struct irq_data *d)
unsigned long flags; unsigned long flags;
u32 val; u32 val;
spin_lock_irqsave(&pctl->lock, flags); raw_spin_lock_irqsave(&pctl->lock, flags);
/* Mask the IRQ */ /* Mask the IRQ */
val = readl(pctl->membase + reg); val = readl(pctl->membase + reg);
writel(val & ~(1 << idx), pctl->membase + reg); writel(val & ~(1 << idx), pctl->membase + reg);
spin_unlock_irqrestore(&pctl->lock, flags); raw_spin_unlock_irqrestore(&pctl->lock, flags);
} }
static void sunxi_pinctrl_irq_unmask(struct irq_data *d) static void sunxi_pinctrl_irq_unmask(struct irq_data *d)
@ -910,13 +910,13 @@ static void sunxi_pinctrl_irq_unmask(struct irq_data *d)
unsigned long flags; unsigned long flags;
u32 val; u32 val;
spin_lock_irqsave(&pctl->lock, flags); raw_spin_lock_irqsave(&pctl->lock, flags);
/* Unmask the IRQ */ /* Unmask the IRQ */
val = readl(pctl->membase + reg); val = readl(pctl->membase + reg);
writel(val | (1 << idx), pctl->membase + reg); writel(val | (1 << idx), pctl->membase + reg);
spin_unlock_irqrestore(&pctl->lock, flags); raw_spin_unlock_irqrestore(&pctl->lock, flags);
} }
static void sunxi_pinctrl_irq_ack_unmask(struct irq_data *d) static void sunxi_pinctrl_irq_ack_unmask(struct irq_data *d)
@ -1253,7 +1253,7 @@ int sunxi_pinctrl_init_with_variant(struct platform_device *pdev,
return -ENOMEM; return -ENOMEM;
platform_set_drvdata(pdev, pctl); platform_set_drvdata(pdev, pctl);
spin_lock_init(&pctl->lock); raw_spin_lock_init(&pctl->lock);
res = platform_get_resource(pdev, IORESOURCE_MEM, 0); res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
pctl->membase = devm_ioremap_resource(&pdev->dev, res); pctl->membase = devm_ioremap_resource(&pdev->dev, res);

2
drivers/pinctrl/sunxi/pinctrl-sunxi.h
View file

@ -134,7 +134,7 @@ struct sunxi_pinctrl {
unsigned ngroups; unsigned ngroups;
int *irq; int *irq;
unsigned *irq_array; unsigned *irq_array;
spinlock_t lock; raw_spinlock_t lock;
struct pinctrl_dev *pctl_dev; struct pinctrl_dev *pctl_dev;
unsigned long variant; unsigned long variant;
}; };