drm/i915/bxt: add display initialize/uninitialize sequence (CDCLK)
Add CDCLK specific display clock initialization sequence as per BSpec. Note that the CDCLK initialization/uninitialization are done at their current place only for simplicity, in a future patch - when more of the runtime PM features will be enabled - these will be moved to power well#1 and modeset encoder enabling/disabling hooks respectively. This also means that atm dynamic power gating power well #1 is effectively disabled. The call to uninitialize CDCLK during system/runtime suspend will be added later in this patchset. v1: Added function definitions in header files v2: Imre's review comments addressed - Moved CDCLK related definitions to i915_reg.h - Removed defintions for CDCLK frequency - Split uninit_cdclk() by adding a phy_uninit function - Calculate freq and decimal based on input frequency - Program SSA precharge based on input frequency - Use wait_for 1ms instead 200us udelay for DE PLL locking - Removed initial value for divider, freq, decimal, ratio. - Replaced polling loops with wait_for - Parameterized latency optim setting - Fix the parts where DE PLL has to be disabled. - Call CDCLK selection from mode set v3: (imre) - add note about the plan to move the cdclk/phy init to a better place - take rps.hw_lock around pcode access - move DE PLL register macros here from another patch since they are used here first - add BXT_ prefix to CDCLK flags - add missing masking when programming CDCLK_FREQ_DECIMAL v4: (ville) - split the CDCLK/PHY parts into two patches, update commit message accordingly - s/DISPLAY_PCU_CONTROL/HSW_PCODE_DE_WRITE_FREQ_REQ/ - simplify BXT_DE_PLL_RATIO macros - fix BXT_DE_PLL_RATIO_MASK - s/bxt_select_cdclk_freq/broxton_set_cdclk_freq/ - move cdclk init/uninit/set code from intel_ddi.c to intel_display.c - remove redundant code comments for broxton_set_cdclk_freq() - sanitize fixed point<->integer frequency value conversion - use DRM_ERROR instead of WARN - do RMW when programming BXT_DE_PLL_CTL for safety - add note about PLL lock timeout being exactly 200us - make PCU error messages more descriptive - instead of using 0 freq to mean PLL off/bypass freq use 19200 for clarity, as the latter one is the actual rate - simplify pcode programming, removing duplicated sandybridge_pcode_write() call - sanitize code flow, remove unnecessary scratch vars in broxton_set_cdclk() (imre) - Remove bound check for maxmimum freq to match current code. This check will be added later at a more proper platform independent place once atomic support lands. - add note to remove freq guard band which isn't needed on BXT - add note to reduce freq to minimum if no pipe is enabled - combine broxton_modeset_global_pipes() with valleyview_modeset_global_pipes() Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> (v2) Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Vandana Kannan
Daniel Vetter
parent
164dfd2877
commit
f8437dd1b5
4 changed files with 248 additions and 3 deletions
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@ -5451,6 +5451,9 @@ enum skl_disp_power_wells {
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#define DISP_FBC_WM_DIS (1<<15)
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#define DISP_ARB_CTL2 0x45004
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#define DISP_DATA_PARTITION_5_6 (1<<6)
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#define DBUF_CTL 0x45008
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#define DBUF_POWER_REQUEST (1<<31)
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#define DBUF_POWER_STATE (1<<30)
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#define GEN7_MSG_CTL 0x45010
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#define WAIT_FOR_PCH_RESET_ACK (1<<1)
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#define WAIT_FOR_PCH_FLR_ACK (1<<0)
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@ -6402,6 +6405,7 @@ enum skl_disp_power_wells {
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#define GEN6_PCODE_WRITE_D_COMP 0x11
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#define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5)
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#define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245)
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#define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17
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#define DISPLAY_IPS_CONTROL 0x19
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#define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A
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#define GEN6_PCODE_DATA 0x138128
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@ -6873,6 +6877,13 @@ enum skl_disp_power_wells {
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#define CDCLK_FREQ_675_617 (3<<26)
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#define CDCLK_FREQ_DECIMAL_MASK (0x7ff)
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#define BXT_CDCLK_CD2X_DIV_SEL_MASK (3<<22)
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#define BXT_CDCLK_CD2X_DIV_SEL_1 (0<<22)
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#define BXT_CDCLK_CD2X_DIV_SEL_1_5 (1<<22)
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#define BXT_CDCLK_CD2X_DIV_SEL_2 (2<<22)
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#define BXT_CDCLK_CD2X_DIV_SEL_4 (3<<22)
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#define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1<<16)
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/* LCPLL_CTL */
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#define LCPLL1_CTL 0x46010
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#define LCPLL2_CTL 0x46014
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@ -6937,6 +6948,15 @@ enum skl_disp_power_wells {
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#define GET_CFG_CR1_REG(id) (DPLL1_CFGCR1 + (id - SKL_DPLL1) * 8)
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#define GET_CFG_CR2_REG(id) (DPLL1_CFGCR2 + (id - SKL_DPLL1) * 8)
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/* BXT display engine PLL */
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#define BXT_DE_PLL_CTL 0x6d000
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#define BXT_DE_PLL_RATIO(x) (x) /* {60,65,100} * 19.2MHz */
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#define BXT_DE_PLL_RATIO_MASK 0xff
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#define BXT_DE_PLL_ENABLE 0x46070
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#define BXT_DE_PLL_PLL_ENABLE (1 << 31)
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#define BXT_DE_PLL_LOCK (1 << 30)
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/* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,
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* since on HSW we can't write to it using I915_WRITE. */
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#define D_COMP_HSW (MCHBAR_MIRROR_BASE_SNB + 0x5F0C)
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@ -1880,6 +1880,8 @@ void intel_ddi_pll_init(struct drm_device *dev)
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if (IS_SKYLAKE(dev)) {
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if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
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DRM_ERROR("LCPLL1 is disabled\n");
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} else if (IS_BROXTON(dev)) {
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broxton_init_cdclk(dev);
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} else {
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/*
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* The LCPLL register should be turned on by the BIOS. For now
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@ -5196,6 +5196,181 @@ static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
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intel_display_set_init_power(dev_priv, false);
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}
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void broxton_set_cdclk(struct drm_device *dev, int frequency)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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uint32_t divider;
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uint32_t ratio;
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uint32_t current_freq;
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int ret;
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/* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
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switch (frequency) {
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case 144000:
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divider = BXT_CDCLK_CD2X_DIV_SEL_4;
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ratio = BXT_DE_PLL_RATIO(60);
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break;
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case 288000:
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divider = BXT_CDCLK_CD2X_DIV_SEL_2;
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ratio = BXT_DE_PLL_RATIO(60);
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break;
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case 384000:
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divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
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ratio = BXT_DE_PLL_RATIO(60);
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break;
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case 576000:
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divider = BXT_CDCLK_CD2X_DIV_SEL_1;
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ratio = BXT_DE_PLL_RATIO(60);
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break;
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case 624000:
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divider = BXT_CDCLK_CD2X_DIV_SEL_1;
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ratio = BXT_DE_PLL_RATIO(65);
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break;
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case 19200:
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/*
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* Bypass frequency with DE PLL disabled. Init ratio, divider
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* to suppress GCC warning.
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*/
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ratio = 0;
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divider = 0;
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break;
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default:
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DRM_ERROR("unsupported CDCLK freq %d", frequency);
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return;
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}
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mutex_lock(&dev_priv->rps.hw_lock);
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/* Inform power controller of upcoming frequency change */
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ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
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0x80000000);
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mutex_unlock(&dev_priv->rps.hw_lock);
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if (ret) {
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DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
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ret, frequency);
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return;
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}
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current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
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/* convert from .1 fixpoint MHz with -1MHz offset to kHz */
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current_freq = current_freq * 500 + 1000;
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/*
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* DE PLL has to be disabled when
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* - setting to 19.2MHz (bypass, PLL isn't used)
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* - before setting to 624MHz (PLL needs toggling)
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* - before setting to any frequency from 624MHz (PLL needs toggling)
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*/
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if (frequency == 19200 || frequency == 624000 ||
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current_freq == 624000) {
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I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
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/* Timeout 200us */
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if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
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1))
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DRM_ERROR("timout waiting for DE PLL unlock\n");
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}
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if (frequency != 19200) {
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uint32_t val;
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val = I915_READ(BXT_DE_PLL_CTL);
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val &= ~BXT_DE_PLL_RATIO_MASK;
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val |= ratio;
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I915_WRITE(BXT_DE_PLL_CTL, val);
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I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
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/* Timeout 200us */
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if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
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DRM_ERROR("timeout waiting for DE PLL lock\n");
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val = I915_READ(CDCLK_CTL);
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val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
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val |= divider;
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/*
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* Disable SSA Precharge when CD clock frequency < 500 MHz,
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* enable otherwise.
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*/
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val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
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if (frequency >= 500000)
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val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
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val &= ~CDCLK_FREQ_DECIMAL_MASK;
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/* convert from kHz to .1 fixpoint MHz with -1MHz offset */
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val |= (frequency - 1000) / 500;
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I915_WRITE(CDCLK_CTL, val);
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}
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mutex_lock(&dev_priv->rps.hw_lock);
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ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
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DIV_ROUND_UP(frequency, 25000));
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mutex_unlock(&dev_priv->rps.hw_lock);
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if (ret) {
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DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
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ret, frequency);
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return;
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}
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dev_priv->cdclk_freq = frequency;
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}
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void broxton_init_cdclk(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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uint32_t val;
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/*
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* NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
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* or else the reset will hang because there is no PCH to respond.
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* Move the handshake programming to initialization sequence.
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* Previously was left up to BIOS.
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*/
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val = I915_READ(HSW_NDE_RSTWRN_OPT);
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val &= ~RESET_PCH_HANDSHAKE_ENABLE;
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I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
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/* Enable PG1 for cdclk */
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intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
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/* check if cd clock is enabled */
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if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
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DRM_DEBUG_KMS("Display already initialized\n");
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return;
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}
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/*
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* FIXME:
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* - The initial CDCLK needs to be read from VBT.
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* Need to make this change after VBT has changes for BXT.
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* - check if setting the max (or any) cdclk freq is really necessary
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* here, it belongs to modeset time
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*/
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broxton_set_cdclk(dev, 624000);
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I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
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udelay(10);
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if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
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DRM_ERROR("DBuf power enable timeout!\n");
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}
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void broxton_uninit_cdclk(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
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udelay(10);
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if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
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DRM_ERROR("DBuf power disable timeout!\n");
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/* Set minimum (bypass) frequency, in effect turning off the DE PLL */
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broxton_set_cdclk(dev, 19200);
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intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
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}
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/* returns HPLL frequency in kHz */
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static int valleyview_get_vco(struct drm_i915_private *dev_priv)
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{
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@ -5363,6 +5538,26 @@ static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
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return 200000;
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}
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static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
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int max_pixclk)
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{
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/*
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* FIXME:
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* - remove the guardband, it's not needed on BXT
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* - set 19.2MHz bypass frequency if there are no active pipes
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*/
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if (max_pixclk > 576000*9/10)
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return 624000;
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else if (max_pixclk > 384000*9/10)
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return 576000;
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else if (max_pixclk > 288000*9/10)
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return 384000;
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else if (max_pixclk > 144000*9/10)
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return 288000;
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else
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return 144000;
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}
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/* compute the max pixel clock for new configuration */
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static int intel_mode_max_pixclk(struct drm_atomic_state *state)
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{
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@ -5392,12 +5587,17 @@ static int valleyview_modeset_global_pipes(struct drm_atomic_state *state,
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struct drm_i915_private *dev_priv = to_i915(state->dev);
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struct intel_crtc *intel_crtc;
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int max_pixclk = intel_mode_max_pixclk(state);
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int cdclk;
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if (max_pixclk < 0)
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return max_pixclk;
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if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
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dev_priv->cdclk_freq)
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if (IS_VALLEYVIEW(dev_priv))
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cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
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else
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cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
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if (cdclk == dev_priv->cdclk_freq)
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return 0;
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/* disable/enable all currently active pipes while we change cdclk */
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@ -8827,6 +9027,23 @@ void hsw_disable_pc8(struct drm_i915_private *dev_priv)
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intel_prepare_ddi(dev);
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}
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static void broxton_modeset_global_resources(struct drm_atomic_state *state)
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{
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struct drm_device *dev = state->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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int max_pixclk = intel_mode_max_pixclk(state);
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int req_cdclk;
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/* see the comment in valleyview_modeset_global_resources */
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if (WARN_ON(max_pixclk < 0))
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return;
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req_cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
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if (req_cdclk != dev_priv->cdclk_freq)
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broxton_set_cdclk(dev, req_cdclk);
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}
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static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
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struct intel_crtc_state *crtc_state)
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{
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@ -11983,7 +12200,7 @@ static int __intel_set_mode(struct drm_crtc *crtc,
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* mode set on this crtc. For other crtcs we need to use the
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* adjusted_mode bits in the crtc directly.
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*/
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if (IS_VALLEYVIEW(dev)) {
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if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
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ret = valleyview_modeset_global_pipes(state, &prepare_pipes);
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if (ret)
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goto done;
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@ -14005,6 +14222,9 @@ static void intel_init_display(struct drm_device *dev)
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} else if (IS_VALLEYVIEW(dev)) {
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dev_priv->display.modeset_global_resources =
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valleyview_modeset_global_resources;
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} else if (IS_BROXTON(dev)) {
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dev_priv->display.modeset_global_resources =
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broxton_modeset_global_resources;
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}
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switch (INTEL_INFO(dev)->gen) {
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@ -1112,6 +1112,9 @@ void intel_prepare_reset(struct drm_device *dev);
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void intel_finish_reset(struct drm_device *dev);
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void hsw_enable_pc8(struct drm_i915_private *dev_priv);
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void hsw_disable_pc8(struct drm_i915_private *dev_priv);
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void broxton_init_cdclk(struct drm_device *dev);
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void broxton_uninit_cdclk(struct drm_device *dev);
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void broxton_set_cdclk(struct drm_device *dev, int frequency);
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void intel_dp_get_m_n(struct intel_crtc *crtc,
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struct intel_crtc_state *pipe_config);
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void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
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