ARM: SPEAr13xx: Pass DW DMAC platform data from DT
This patch adds dw_dmac's platform data to DT node. It also creates slave info node for SPEAr13xx, for the devices which were using dw_dmac. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
This commit is contained in:
Viresh Kumar
Vinod Koul
parent
a9ddb575d6
commit
f9965aa207
6 changed files with 72 additions and 80 deletions
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@ -88,6 +88,25 @@
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status = "disabled";
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};
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dma@ea800000 {
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slave_info {
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uart1_tx {
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bus_id = "uart1_tx";
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cfg_hi = <0x6000>; /* 0xC << 11 */
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cfg_lo = <0>;
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src_master = <0>;
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dst_master = <1>;
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};
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uart1_tx {
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bus_id = "uart1_tx";
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cfg_hi = <0x680>; /* 0xD << 7 */
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cfg_lo = <0>;
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src_master = <1>;
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dst_master = <0>;
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};
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};
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};
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spi1: spi@5d400000 {
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compatible = "arm,pl022", "arm,primecell";
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reg = <0x5d400000 0x1000>;
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@ -105,6 +105,37 @@
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reg = <0xea800000 0x1000>;
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interrupts = <0 19 0x4>;
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status = "disabled";
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nr_channels = <8>;
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chan_allocation_order = <1>;
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chan_priority = <1>;
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block_size = <0xfff>;
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nr_masters = <2>;
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data_width = <3 3 0 0>;
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slave_info {
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ssp0_tx {
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bus_id = "ssp0_tx";
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cfg_hi = <0x2000>; /* 0x4 << 11 */
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cfg_lo = <0>;
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src_master = <0>;
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dst_master = <0>;
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};
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ssp0_rx {
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bus_id = "ssp0_rx";
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cfg_hi = <0x280>; /* 0x5 << 7 */
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cfg_lo = <0>;
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src_master = <0>;
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dst_master = <0>;
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};
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cf {
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bus_id = "cf";
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cfg_hi = <0>;
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cfg_lo = <0>;
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src_master = <0>;
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dst_master = <0>;
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};
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};
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};
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dma@eb000000 {
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@ -112,6 +143,13 @@
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reg = <0xeb000000 0x1000>;
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interrupts = <0 59 0x4>;
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status = "disabled";
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nr_channels = <8>;
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chan_allocation_order = <1>;
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chan_priority = <1>;
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block_size = <0xfff>;
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nr_masters = <2>;
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data_width = <3 3 0 0>;
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};
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fsmc: flash@b0000000 {
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@ -43,8 +43,6 @@
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#define VA_L2CC_BASE IOMEM(UL(0xFB000000))
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/* others */
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#define DMAC0_BASE UL(0xEA800000)
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#define DMAC1_BASE UL(0xEB000000)
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#define MCIF_CF_BASE UL(0xB2800000)
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/* Debug uart for linux, will be used for debug and uncompress messages */
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@ -36,7 +36,7 @@
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static struct arasan_cf_pdata cf_pdata = {
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.cf_if_clk = CF_IF_CLK_166M,
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.quirk = CF_BROKEN_UDMA,
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.dma_priv = &cf_dma_priv,
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.dma_priv = "cf",
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};
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/* ssp device registration */
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@ -47,10 +47,7 @@ static struct pl022_ssp_controller ssp1_plat_data = {
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/* Add SPEAr1310 auxdata to pass platform data */
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static struct of_dev_auxdata spear1310_auxdata_lookup[] __initdata = {
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OF_DEV_AUXDATA("arasan,cf-spear1340", MCIF_CF_BASE, NULL, &cf_pdata),
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OF_DEV_AUXDATA("snps,dma-spear1340", DMAC0_BASE, NULL, &dmac_plat_data),
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OF_DEV_AUXDATA("snps,dma-spear1340", DMAC1_BASE, NULL, &dmac_plat_data),
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OF_DEV_AUXDATA("arm,pl022", SSP_BASE, NULL, &pl022_plat_data),
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OF_DEV_AUXDATA("arm,pl022", SPEAR1310_SSP1_BASE, NULL, &ssp1_plat_data),
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{}
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};
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@ -18,9 +18,9 @@
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#include <linux/delay.h>
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#include <linux/dw_dmac.h>
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#include <linux/of_platform.h>
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#include <linux/pata_arasan_cf_data.h>
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#include <asm/hardware/gic.h>
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#include <asm/mach/arch.h>
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#include <mach/dma.h>
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#include <mach/generic.h>
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#include <mach/spear.h>
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@ -78,26 +78,16 @@
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(SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
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SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
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static struct dw_dma_slave uart1_dma_param[] = {
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{
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/* Tx */
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.cfg_hi = DWC_CFGH_DST_PER(SPEAR1340_DMA_REQ_UART1_TX),
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.cfg_lo = 0,
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.src_master = DMA_MASTER_MEMORY,
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.dst_master = SPEAR1340_DMA_MASTER_UART1,
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}, {
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/* Rx */
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.cfg_hi = DWC_CFGH_SRC_PER(SPEAR1340_DMA_REQ_UART1_RX),
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.cfg_lo = 0,
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.src_master = SPEAR1340_DMA_MASTER_UART1,
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.dst_master = DMA_MASTER_MEMORY,
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}
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static struct amba_pl011_data uart1_data = {
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.dma_filter = dw_dma_generic_filter,
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.dma_tx_param = "uart1_tx",
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.dma_rx_param = "uart1_rx",
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};
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static struct amba_pl011_data uart1_data = {
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.dma_filter = dw_dma_filter,
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.dma_tx_param = &uart1_dma_param[0],
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.dma_rx_param = &uart1_dma_param[1],
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static struct arasan_cf_pdata cf_pdata = {
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.cf_if_clk = CF_IF_CLK_166M,
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.quirk = CF_BROKEN_UDMA,
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.dma_priv = "cf",
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};
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/* SATA device registration */
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@ -158,11 +148,8 @@ static struct ahci_platform_data sata_pdata = {
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/* Add SPEAr1340 auxdata to pass platform data */
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static struct of_dev_auxdata spear1340_auxdata_lookup[] __initdata = {
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OF_DEV_AUXDATA("arasan,cf-spear1340", MCIF_CF_BASE, NULL, &cf_dma_priv),
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OF_DEV_AUXDATA("snps,dma-spear1340", DMAC0_BASE, NULL, &dmac_plat_data),
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OF_DEV_AUXDATA("snps,dma-spear1340", DMAC1_BASE, NULL, &dmac_plat_data),
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OF_DEV_AUXDATA("arasan,cf-spear1340", MCIF_CF_BASE, NULL, &cf_pdata),
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OF_DEV_AUXDATA("arm,pl022", SSP_BASE, NULL, &pl022_plat_data),
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OF_DEV_AUXDATA("snps,spear-ahci", SPEAR1340_SATA_BASE, NULL,
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&sata_pdata),
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OF_DEV_AUXDATA("arm,pl011", SPEAR1340_UART1_BASE, NULL, &uart1_data),
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@ -22,63 +22,16 @@
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#include <asm/hardware/gic.h>
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#include <asm/mach/map.h>
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#include <asm/smp_twd.h>
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#include <mach/dma.h>
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#include <mach/generic.h>
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#include <mach/spear.h>
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/* common dw_dma filter routine to be used by peripherals */
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bool dw_dma_filter(struct dma_chan *chan, void *slave)
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{
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struct dw_dma_slave *dws = (struct dw_dma_slave *)slave;
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if (chan->device->dev == dws->dma_dev) {
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chan->private = slave;
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return true;
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} else {
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return false;
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}
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}
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/* ssp device registration */
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static struct dw_dma_slave ssp_dma_param[] = {
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{
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/* Tx */
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.cfg_hi = DWC_CFGH_DST_PER(DMA_REQ_SSP0_TX),
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.cfg_lo = 0,
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.src_master = DMA_MASTER_MEMORY,
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.dst_master = DMA_MASTER_SSP0,
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}, {
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/* Rx */
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.cfg_hi = DWC_CFGH_SRC_PER(DMA_REQ_SSP0_RX),
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.cfg_lo = 0,
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.src_master = DMA_MASTER_SSP0,
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.dst_master = DMA_MASTER_MEMORY,
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}
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};
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struct pl022_ssp_controller pl022_plat_data = {
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.enable_dma = 1,
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.dma_filter = dw_dma_filter,
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.dma_rx_param = &ssp_dma_param[1],
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.dma_tx_param = &ssp_dma_param[0],
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};
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/* CF device registration */
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struct dw_dma_slave cf_dma_priv = {
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.cfg_hi = 0,
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.cfg_lo = 0,
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.src_master = 0,
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.dst_master = 0,
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};
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/* dmac device registeration */
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struct dw_dma_platform_data dmac_plat_data = {
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.nr_channels = 8,
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.chan_allocation_order = CHAN_ALLOCATION_DESCENDING,
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.chan_priority = CHAN_PRIORITY_DESCENDING,
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.block_size = 4095U,
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.nr_masters = 2,
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.data_width = { 3, 3, 0, 0 },
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.dma_filter = dw_dma_generic_filter,
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.dma_rx_param = "ssp0_rx",
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.dma_tx_param = "ssp0_tx",
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.num_chipselect = 3,
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};
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void __init spear13xx_l2x0_init(void)
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