x86: x2apic, IR: Clean up X86_X2APIC and INTR_REMAP config checks
Add x2apic_supported() to clean up CONFIG_X86_X2APIC checks. Fix CONFIG_INTR_REMAP checks. [ Impact: cleanup ] Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com> Cc: dwmw2@infradead.org Cc: Suresh Siddha <suresh.b.siddha@intel.com> Cc: Weidong Han <weidong.han@intel.com> LKML-Reference: <20090420200450.128993000@linux-os.sc.intel.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
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667c5296cc
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fc1edaf9e7
7 changed files with 21 additions and 48 deletions
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@ -107,8 +107,7 @@ extern u32 native_safe_apic_wait_icr_idle(void);
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extern void native_apic_icr_write(u32 low, u32 id);
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extern u64 native_apic_icr_read(void);
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#define EIM_8BIT_APIC_ID 0
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#define EIM_32BIT_APIC_ID 1
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extern int x2apic_mode;
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#ifdef CONFIG_X86_X2APIC
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/*
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@ -166,7 +165,7 @@ static inline u64 native_x2apic_icr_read(void)
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return val;
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}
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extern int x2apic, x2apic_phys;
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extern int x2apic_phys;
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extern void check_x2apic(void);
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extern void enable_x2apic(void);
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extern void x2apic_icr_write(u32 low, u32 id);
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@ -182,6 +181,8 @@ static inline int x2apic_enabled(void)
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return 1;
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return 0;
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}
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#define x2apic_supported() (cpu_has_x2apic)
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#else
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static inline void check_x2apic(void)
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{
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@ -194,9 +195,8 @@ static inline int x2apic_enabled(void)
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return 0;
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}
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#define x2apic 0
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#define x2apic_preenabled 0
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#define x2apic_supported() 0
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#endif
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extern void enable_IR_x2apic(void);
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@ -161,7 +161,6 @@ extern int io_apic_set_pci_routing(int ioapic, int pin, int irq,
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extern int (*ioapic_renumber_irq)(int ioapic, int irq);
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extern void ioapic_init_mappings(void);
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#ifdef CONFIG_X86_64
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extern struct IO_APIC_route_entry **alloc_ioapic_entries(void);
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extern void free_ioapic_entries(struct IO_APIC_route_entry **ioapic_entries);
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extern int save_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries);
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@ -169,7 +168,6 @@ extern void mask_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries);
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extern int restore_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries);
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extern void reinit_intr_remapped_IO_APIC(int intr_remapping,
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struct IO_APIC_route_entry **ioapic_entries);
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#endif
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extern void probe_nr_irqs_gsi(void);
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@ -1,6 +1,6 @@
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#ifndef _ASM_X86_IRQ_REMAPPING_H
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#define _ASM_X86_IRQ_REMAPPING_H
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#define IRTE_DEST(dest) ((x2apic) ? dest : dest << 8)
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#define IRTE_DEST(dest) ((x2apic_mode) ? dest : dest << 8)
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#endif /* _ASM_X86_IRQ_REMAPPING_H */
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@ -134,8 +134,8 @@ static __init int setup_apicpmtimer(char *s)
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__setup("apicpmtimer", setup_apicpmtimer);
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#endif
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int x2apic_mode;
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#ifdef CONFIG_X86_X2APIC
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int x2apic;
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/* x2apic enabled before OS handover */
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static int x2apic_preenabled;
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static int disable_x2apic;
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@ -858,7 +858,7 @@ void clear_local_APIC(void)
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u32 v;
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/* APIC hasn't been mapped yet */
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if (!x2apic && !apic_phys)
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if (!x2apic_mode && !apic_phys)
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return;
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maxlvt = lapic_get_maxlvt();
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@ -1330,7 +1330,7 @@ void check_x2apic(void)
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{
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if (x2apic_enabled()) {
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pr_info("x2apic enabled by BIOS, switching to x2apic ops\n");
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x2apic_preenabled = x2apic = 1;
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x2apic_preenabled = x2apic_mode = 1;
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}
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}
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@ -1338,7 +1338,7 @@ void enable_x2apic(void)
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{
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int msr, msr2;
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if (!x2apic)
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if (!x2apic_mode)
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return;
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rdmsr(MSR_IA32_APICBASE, msr, msr2);
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@ -1390,25 +1390,17 @@ void __init enable_IR_x2apic(void)
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mask_IO_APIC_setup(ioapic_entries);
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mask_8259A();
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#ifdef CONFIG_X86_X2APIC
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if (cpu_has_x2apic)
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ret = enable_intr_remapping(EIM_32BIT_APIC_ID);
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else
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#endif
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ret = enable_intr_remapping(EIM_8BIT_APIC_ID);
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ret = enable_intr_remapping(x2apic_supported());
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if (ret)
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goto end_restore;
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pr_info("Enabled Interrupt-remapping\n");
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#ifdef CONFIG_X86_X2APIC
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if (cpu_has_x2apic && !x2apic) {
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x2apic = 1;
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if (x2apic_supported() && !x2apic_mode) {
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x2apic_mode = 1;
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enable_x2apic();
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pr_info("Enabled x2apic\n");
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}
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#endif
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end_restore:
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if (ret)
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@ -1576,7 +1568,7 @@ void __init early_init_lapic_mapping(void)
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*/
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void __init init_apic_mappings(void)
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{
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if (x2apic) {
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if (x2apic_mode) {
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boot_cpu_physical_apicid = read_apic_id();
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return;
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}
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@ -2010,10 +2002,10 @@ static int lapic_suspend(struct sys_device *dev, pm_message_t state)
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local_irq_save(flags);
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disable_local_APIC();
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#ifdef CONFIG_INTR_REMAP
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if (intr_remapping_enabled)
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disable_intr_remapping();
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#endif
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local_irq_restore(flags);
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return 0;
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}
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@ -2023,8 +2015,6 @@ static int lapic_resume(struct sys_device *dev)
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unsigned int l, h;
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unsigned long flags;
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int maxlvt;
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#ifdef CONFIG_INTR_REMAP
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int ret;
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struct IO_APIC_route_entry **ioapic_entries = NULL;
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@ -2050,17 +2040,8 @@ static int lapic_resume(struct sys_device *dev)
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mask_8259A();
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}
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if (x2apic)
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if (x2apic_mode)
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enable_x2apic();
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#else
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if (!apic_pm_state.active)
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return 0;
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local_irq_save(flags);
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if (x2apic)
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enable_x2apic();
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#endif
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else {
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/*
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* Make sure the APICBASE points to the right address
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@ -2098,18 +2079,12 @@ static int lapic_resume(struct sys_device *dev)
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apic_write(APIC_ESR, 0);
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apic_read(APIC_ESR);
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#ifdef CONFIG_INTR_REMAP
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if (intr_remapping_enabled) {
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if (x2apic)
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reenable_intr_remapping(EIM_32BIT_APIC_ID);
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else
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reenable_intr_remapping(EIM_8BIT_APIC_ID);
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reenable_intr_remapping(x2apic_mode);
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unmask_8259A();
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restore_IO_APIC_setup(ioapic_entries);
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free_ioapic_entries(ioapic_entries);
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}
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#endif
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local_irq_restore(flags);
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@ -736,7 +736,6 @@ static int __init ioapic_pirq_setup(char *str)
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__setup("pirq=", ioapic_pirq_setup);
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#endif /* CONFIG_X86_32 */
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#ifdef CONFIG_INTR_REMAP
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struct IO_APIC_route_entry **alloc_ioapic_entries(void)
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{
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int apic;
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@ -857,7 +856,6 @@ void free_ioapic_entries(struct IO_APIC_route_entry **ioapic_entries)
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kfree(ioapic_entries);
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}
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#endif
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/*
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* Find the IRQ entry number of a certain pin.
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@ -50,7 +50,7 @@ static struct apic *apic_probe[] __initdata = {
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void __init default_setup_apic_routing(void)
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{
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#ifdef CONFIG_X86_X2APIC
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if (x2apic && (apic != &apic_x2apic_phys &&
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if (x2apic_mode && (apic != &apic_x2apic_phys &&
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#ifdef CONFIG_X86_UV
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apic != &apic_x2apic_uv_x &&
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#endif
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@ -158,6 +158,8 @@ static inline struct intel_iommu *map_ioapic_to_ir(int apic)
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}
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#define irq_remapped(irq) (0)
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#define enable_intr_remapping(mode) (-1)
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#define disable_intr_remapping() (0)
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#define reenable_intr_remapping(mode) (0)
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#define intr_remapping_enabled (0)
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#endif
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