Merge branch 'for-next' of http://git.agner.ch/git/linux-drm-fsl-dcu into drm-next
fsl-dcu pixel clock polarity support * 'for-next' of http://git.agner.ch/git/linux-drm-fsl-dcu: drm/fsl-dcu: use bus_flags for pixel clock polarity drm: introduce bus_flags in drm_display_info
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commit
fd50c3a032
4 changed files with 20 additions and 3 deletions
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@ -66,6 +66,7 @@ static void fsl_dcu_drm_crtc_mode_set_nofb(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
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struct drm_connector *con = &fsl_dev->connector.base;
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struct drm_display_mode *mode = &crtc->state->mode;
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unsigned int hbp, hfp, hsw, vbp, vfp, vsw, index, pol = 0;
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@ -80,6 +81,10 @@ static void fsl_dcu_drm_crtc_mode_set_nofb(struct drm_crtc *crtc)
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vfp = mode->vsync_start - mode->vdisplay;
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vsw = mode->vsync_end - mode->vsync_start;
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/* INV_PXCK as default (most display sample data on rising edge) */
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if (!(con->display_info.bus_flags & DRM_BUS_FLAG_PIXDATA_POSEDGE))
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pol |= DCU_SYN_POL_INV_PXCK;
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if (mode->flags & DRM_MODE_FLAG_NHSYNC)
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pol |= DCU_SYN_POL_INV_HS_LOW;
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@ -47,8 +47,8 @@
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#define DCU_VSYN_PARA_FP(x) (x)
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#define DCU_SYN_POL 0x0024
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#define DCU_SYN_POL_INV_PXCK_FALL (0 << 6)
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#define DCU_SYN_POL_NEG_REMAIN (0 << 5)
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#define DCU_SYN_POL_INV_PXCK BIT(6)
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#define DCU_SYN_POL_NEG BIT(5)
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#define DCU_SYN_POL_INV_VS_LOW BIT(1)
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#define DCU_SYN_POL_INV_HS_LOW BIT(0)
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@ -72,6 +72,7 @@ struct panel_desc {
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} delay;
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u32 bus_format;
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u32 bus_flags;
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};
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struct panel_simple {
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@ -144,6 +145,7 @@ static int panel_simple_get_fixed_modes(struct panel_simple *panel)
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if (panel->desc->bus_format)
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drm_display_info_set_bus_formats(&connector->display_info,
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&panel->desc->bus_format, 1);
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connector->display_info.bus_flags = panel->desc->bus_flags;
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return num;
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}
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@ -1051,7 +1053,8 @@ static const struct panel_desc nec_nl4827hc19_05b = {
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.width = 95,
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.height = 54,
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},
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.bus_format = MEDIA_BUS_FMT_RGB888_1X24
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.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
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.bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE,
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};
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static const struct display_timing okaya_rs800480t_7x0gp_timing = {
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@ -118,6 +118,14 @@ enum subpixel_order {
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#define DRM_COLOR_FORMAT_RGB444 (1<<0)
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#define DRM_COLOR_FORMAT_YCRCB444 (1<<1)
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#define DRM_COLOR_FORMAT_YCRCB422 (1<<2)
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#define DRM_BUS_FLAG_DE_LOW (1<<0)
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#define DRM_BUS_FLAG_DE_HIGH (1<<1)
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/* drive data on pos. edge */
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#define DRM_BUS_FLAG_PIXDATA_POSEDGE (1<<2)
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/* drive data on neg. edge */
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#define DRM_BUS_FLAG_PIXDATA_NEGEDGE (1<<3)
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/*
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* Describes a given display (e.g. CRT or flat panel) and its limitations.
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*/
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@ -139,6 +147,7 @@ struct drm_display_info {
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const u32 *bus_formats;
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unsigned int num_bus_formats;
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u32 bus_flags;
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/* Mask of supported hdmi deep color modes */
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u8 edid_hdmi_dc_modes;
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