ARM: tegra: move resume vector define to irammap.h
irammap.h's purpose is to define the layout/usage of IRAM. As such, TEGRA_IRAM_CODE_AREA should have been added there rather than iomap.h. Move the define, and rename it something more descriptive. Cc: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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6 changed files with 17 additions and 11 deletions
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@ -24,8 +24,6 @@
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#define TEGRA_IRAM_BASE 0x40000000
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#define TEGRA_IRAM_BASE 0x40000000
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#define TEGRA_IRAM_SIZE SZ_256K
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#define TEGRA_IRAM_SIZE SZ_256K
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#define TEGRA_IRAM_CODE_AREA (TEGRA_IRAM_BASE + SZ_4K)
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#define TEGRA_HOST1X_BASE 0x50000000
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#define TEGRA_HOST1X_BASE 0x50000000
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#define TEGRA_HOST1X_SIZE 0x24000
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#define TEGRA_HOST1X_SIZE 0x24000
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@ -23,4 +23,10 @@
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#define TEGRA_IRAM_RESET_HANDLER_OFFSET 0
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#define TEGRA_IRAM_RESET_HANDLER_OFFSET 0
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#define TEGRA_IRAM_RESET_HANDLER_SIZE SZ_1K
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#define TEGRA_IRAM_RESET_HANDLER_SIZE SZ_1K
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/*
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* This area is used for LPx resume vector, only while LPx power state is
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* active. At other times, the AVP may use this area for arbitrary purposes
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*/
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#define TEGRA_IRAM_LPx_RESUME_AREA (TEGRA_IRAM_BASE + SZ_4K)
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#endif
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#endif
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@ -263,10 +263,10 @@ static void tegra_suspend_enter_lp1(void)
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tegra_pmc_suspend();
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tegra_pmc_suspend();
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/* copy the reset vector & SDRAM shutdown code into IRAM */
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/* copy the reset vector & SDRAM shutdown code into IRAM */
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memcpy(iram_save_addr, IO_ADDRESS(TEGRA_IRAM_CODE_AREA),
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memcpy(iram_save_addr, IO_ADDRESS(TEGRA_IRAM_LPx_RESUME_AREA),
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iram_save_size);
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memcpy(IO_ADDRESS(TEGRA_IRAM_CODE_AREA), tegra_lp1_iram.start_addr,
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iram_save_size);
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iram_save_size);
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memcpy(IO_ADDRESS(TEGRA_IRAM_LPx_RESUME_AREA),
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tegra_lp1_iram.start_addr, iram_save_size);
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*((u32 *)tegra_cpu_lp1_mask) = 1;
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*((u32 *)tegra_cpu_lp1_mask) = 1;
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}
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}
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@ -276,7 +276,7 @@ static void tegra_suspend_exit_lp1(void)
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tegra_pmc_resume();
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tegra_pmc_resume();
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/* restore IRAM */
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/* restore IRAM */
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memcpy(IO_ADDRESS(TEGRA_IRAM_CODE_AREA), iram_save_addr,
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memcpy(IO_ADDRESS(TEGRA_IRAM_LPx_RESUME_AREA), iram_save_addr,
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iram_save_size);
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iram_save_size);
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*(u32 *)tegra_cpu_lp1_mask = 0;
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*(u32 *)tegra_cpu_lp1_mask = 0;
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@ -82,7 +82,7 @@ void __init tegra_cpu_reset_handler_init(void)
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#ifdef CONFIG_PM_SLEEP
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#ifdef CONFIG_PM_SLEEP
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__tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_LP1] =
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__tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_LP1] =
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TEGRA_IRAM_CODE_AREA;
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TEGRA_IRAM_LPx_RESUME_AREA;
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__tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_LP2] =
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__tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_LP2] =
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virt_to_phys((void *)tegra_resume);
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virt_to_phys((void *)tegra_resume);
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#endif
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#endif
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@ -25,6 +25,7 @@
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#include <asm/cp15.h>
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#include <asm/cp15.h>
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#include <asm/cache.h>
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#include <asm/cache.h>
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#include "irammap.h"
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#include "sleep.h"
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#include "sleep.h"
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#include "flowctrl.h"
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#include "flowctrl.h"
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@ -235,7 +236,7 @@ ENTRY(tegra20_sleep_core_finish)
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mov32 r0, tegra20_tear_down_core
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mov32 r0, tegra20_tear_down_core
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mov32 r1, tegra20_iram_start
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mov32 r1, tegra20_iram_start
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sub r0, r0, r1
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sub r0, r0, r1
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mov32 r1, TEGRA_IRAM_CODE_AREA
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mov32 r1, TEGRA_IRAM_LPx_RESUME_AREA
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add r0, r0, r1
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add r0, r0, r1
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mov pc, r3
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mov pc, r3
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@ -328,7 +329,7 @@ tegra20_iram_start:
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* The physical address of tegra_resume expected to be stored in
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* The physical address of tegra_resume expected to be stored in
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* PMC_SCRATCH41.
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* PMC_SCRATCH41.
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*
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*
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* NOTE: THIS *MUST* BE RELOCATED TO TEGRA_IRAM_CODE_AREA.
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* NOTE: THIS *MUST* BE RELOCATED TO TEGRA_IRAM_LPx_RESUME_AREA.
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*/
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*/
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ENTRY(tegra20_lp1_reset)
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ENTRY(tegra20_lp1_reset)
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/*
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/*
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@ -20,6 +20,7 @@
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#include <asm/asm-offsets.h>
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#include <asm/asm-offsets.h>
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#include <asm/cache.h>
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#include <asm/cache.h>
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#include "irammap.h"
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#include "fuse.h"
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#include "fuse.h"
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#include "sleep.h"
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#include "sleep.h"
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#include "flowctrl.h"
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#include "flowctrl.h"
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@ -262,7 +263,7 @@ ENTRY(tegra30_sleep_core_finish)
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mov32 r0, tegra30_tear_down_core
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mov32 r0, tegra30_tear_down_core
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mov32 r1, tegra30_iram_start
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mov32 r1, tegra30_iram_start
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sub r0, r0, r1
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sub r0, r0, r1
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mov32 r1, TEGRA_IRAM_CODE_AREA
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mov32 r1, TEGRA_IRAM_LPx_RESUME_AREA
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add r0, r0, r1
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add r0, r0, r1
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mov pc, r3
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mov pc, r3
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@ -314,7 +315,7 @@ tegra30_iram_start:
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* The physical address of tegra_resume expected to be stored in
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* The physical address of tegra_resume expected to be stored in
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* PMC_SCRATCH41.
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* PMC_SCRATCH41.
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*
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*
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* NOTE: THIS *MUST* BE RELOCATED TO TEGRA_IRAM_CODE_AREA.
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* NOTE: THIS *MUST* BE RELOCATED TO TEGRA_IRAM_LPx_RESUME_AREA.
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*/
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*/
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ENTRY(tegra30_lp1_reset)
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ENTRY(tegra30_lp1_reset)
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/*
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/*
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