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ARM: tegra30: clocks: Fix pciex clock registration

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Registering pciex as peripheral clock instead of fixed clock
as tegra_perih_reset_assert(deassert) api of this clock api
gives warning and ultimately does not succeed to assert(deassert)

Signed-off-by: Jay Agarwal <jagarwal@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
This commit is contained in:
Jay Agarwal 2013-06-12 12:43:43 +05:30 committed by Mike Turquette
parent 346f372f7b
commit ff49fad1d9
1 changed files with 6 additions and 5 deletions
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11
drivers/clk/tegra/clk-tegra30.c
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@ -1598,6 +1598,12 @@ static void __init tegra30_periph_clk_init(void)
clk_register_clkdev(clk, "afi", "tegra-pcie");
clks[afi] = clk;
/* pciex */
clk = tegra_clk_register_periph_gate("pciex", "pll_e", 0, clk_base, 0,
74, &periph_u_regs, periph_clk_enb_refcnt);
clk_register_clkdev(clk, "pciex", "tegra-pcie");
clks[pciex] = clk;
/* kfuse */
clk = tegra_clk_register_periph_gate("kfuse", "clk_m",
TEGRA_PERIPH_ON_APB,
@ -1716,11 +1722,6 @@ static void __init tegra30_fixed_clk_init(void)
1, 0, &cml_lock);
clk_register_clkdev(clk, "cml1", NULL);
clks[cml1] = clk;
/* pciex */
clk = clk_register_fixed_rate(NULL, "pciex", "pll_e", 0, 100000000);
clk_register_clkdev(clk, "pciex", NULL);
clks[pciex] = clk;
}
static void __init tegra30_osc_clk_init(void)