Commit graph

15 commits

Author SHA1 Message Date
Guo Zeng
a3ff23375a clk: atlas7: fix noc/socket disconnect/reconnect for unit clks
Power management on of NoC(Notwork On Chip) requires that disconnect
and reconnect routine should been done during clk disable/enable.

also there are different types of clocks,
For NoC Macro clocks, write idle_bit and wait for hardward ACK;
For Socket clocks, write idle_bit;
For others, do nothing.

Signed-off-by: Guo Zeng <Guo.Zeng@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-09-29 08:27:14 -07:00
Guo Zeng
1f57d1d88c clk: atlas7: move variable-definition together
re-order the codes more reasonable by moving variable-definition
together.

Signed-off-by: Guo Zeng <Guo.Zeng@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-09-29 08:27:13 -07:00
Guo Zeng
b32a7cc63b clk: atlas7: fix pll missed divide NR in fraction mode
PLL VCO frequency is given by Fvco = Fref * 2 * NF / NR
in integer-N mode, or by Fvco = Fref * SSN / NR in Spread
Spectrum (fractional-N) mode. Thus fix the missing part
of NR

Signed-off-by: Guo Zeng <guo.zeng@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-08-24 16:49:08 -07:00
Guo Zeng
cf8709eabc clk: atlas7: fix bit field and its root clk for coresight_tpiu
bit4 thcpum_cpudiv4_clken 	r/w
thcpum_cpudiv4_clk clock enable (default: 1)
Root clock CPU_CLK must be enabled for this clock to be enabled

bit3 coresight_tpiu_clken 	r/w
coresight_tpiu_clk clock enable (default: 0)
Root clock TPIU_CLK must be enabled for this clock to be enabled

Signed-off-by: Guo Zeng <guo.zeng@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-08-24 16:49:07 -07:00
Yibo Cai
d1ccbddd09 clk: atlas7: replace dto resolution magic number by macro
Signed-off-by: Yibo Cai <yibo.cai@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-08-24 16:49:06 -07:00
Yibo Cai
6132e89aef clk: atlas7: fix integer overflow in dto rate calculation
I cannot believe that I spend quite a lot time in finding this bug.
It seems a pitfall people tend to fall in.

In "int64 = int32 * int32", conversion from 32-bits to 64-bits comes
after the multiplication. So this statement may not work as expected.

Signed-off-by: Yibo Cai <yibo.cai@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-08-24 16:49:06 -07:00
Guo Zeng
b1062298fe clk: atlas7: export mux clks so that consumers can get them
this patch makes mux clks can be referenced by device drivers.

Signed-off-by: Guo Zeng <guo.zeng@csr.com>
Signed-off-by: Barry Song <Barry.Song@csr.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-08-24 16:49:05 -07:00
Guo Zeng
3922107c79 clk: atlas7: add lost pwm unit clks
Signed-off-by: Guo Zeng <Guo.Zeng@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-08-24 16:49:04 -07:00
Stephen Boyd
b17dbff418 clk: sirf: Convert to clk_hw based provider APIs
We're removing struct clk from the clk provider API, so switch
this code to using the clk_hw based provider APIs.

Cc: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-08-24 16:48:54 -07:00
Stephen Boyd
fdb94059d8 clk: sirf: Properly include clk.h
Clock provider drivers generally shouldn't include clk.h because
it's the consumer API. Move the include of clk.h into
clk-common.c because that's the only file that's really using
clk.h, even if it's included into the atlas6 and prima2 files.

Cc: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-20 11:11:13 -07:00
Zhiwu Song
301c5d2940 clk: sirf: add CSR atlas7 clk and reset support
the hardware node includes both clock and reset support, so it
is named as "car".
this patch implements Flexible clocks(mux, divider, gate), Selectable
clock(mux, divider, gate), root clock(gate),leaf clock(gate), others.
it also implements the reset controller functionality.

Signed-off-by: Zhiwu Song <Zhiwu.Song@csr.com>
Signed-off-by: Guo Zeng <Guo.Zeng@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-05-20 15:43:28 -07:00
Stephen Boyd
f53f551b11 clk: sirf: Silence sparse warnings
These are __iomem pointers. Mark them appropriately so we don't
get sparse errors like

drivers/clk/sirf/clk-common.c:60:16: warning: incorrect type in argument 1 (different address spaces)
drivers/clk/sirf/clk-common.c:60:16:    expected void const volatile [noderef] <asn:2>*addr
drivers/clk/sirf/clk-common.c:60:16:    got void *

Cc: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-05-14 17:11:24 -07:00
Krzysztof Kozlowski
45195b8f84 clk: sirf: Constify parent names in clock init data
The array of parent names can be made as array of const pointers to
const strings.

Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-05-05 22:50:48 -07:00
Barry Song
7736692993 clk: sirf: update copyright years to 2014
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-03-26 21:47:35 -07:00
Barry Song
7bf21bc81f clk: sirf: re-arch to make the codes support both prima2 and atlas6
sirfprima2 and sirfatlas6 are two different SoCs in CSR SiRF series. for
prima2 and atlas6, there are many shared clocks but there are still
some different register layout and hardware clocks, then result in
different clock table.

here we re-arch the driver to
1. clk-common.c provides common clocks for prima2 and atlas6,
2. clk-prima2.h describles registers of prima2 and clk-prima2.c provides
prima2 specific clocks and clock table.
3. clk-atlas6.h describles registers of atlas6 and clk-atlas6.c provides
atlas6 specific clocks and clock table.
4. clk.h and clk.c expose external interfaces and provide uniform entry
for both prima2 and atlas6.

so both prima2 and atlas6 will get support by drivers/clk/sirf.

Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Rongjun Ying <Rongjun.Ying@csr.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-01-16 12:00:53 -08:00