4.10, please pull the following:
- Robin updates the Northstart 2 DTS to use the generic IOMMU binding
- Scott renames the Broadcom Northstar 2 binding document to use a standard name
including the brcm vendor prefix
- Kamal adds the QSPI Device Tree node to the Northstar 2 SoC and updates the
Northstar 2 SVK reference board DTS file with it enabled.
- Rob adds the Device Tree node for the Broadcom PDC (mailbox) hardware to the
Northstar 2 SoC
- Jon enables the SDIO1 block and adds proper PCIe PHYs Device Tree nodes to the
Northstar 2 SoC
- Ray adds required properties NAND controller properties to make NAND work on
the Northstar 2 SVK board, this was submitted as a 4.9 fixes and is included
here to resolve DTS file merges
- Andrea removes an incorrect power LED from the Raspberry Pi 3 DTS
- Andreas fixes the compatible string for the BCM2837 (Raspberry Pi 3)
- Eric defines standard pinctrl groups in the BCM2835 GPIO node
- Gerd adds definitions for the pinctrl groups and updates the PWM, I2C and SDHCI nodes
to use their appropriate pinctrl functions
- Linus adds names for the Raspberry Pi GPIO lines based on the datasheet
- Martin adds the DT binding and nodes for the Raspberry Pi firmware thermal block
- Stefan fixes a few typos with respect to the BCM2835 mailbox binding example and
Device Tree nodes he also uses the proper DTSI file to define the USB host mode
for the USB Device Tree nodes
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Merge tag 'arm-soc/for-4.10/devicetree-arm64' of http://github.com/Broadcom/stblinux into next/dt64
Pull "Broadcom devicetree-arm64 changes for 4.10" from Florian Fainelli:
This pull request contains Broadcom ARM64 based SoC Device Tree changes for
4.10, please pull the following:
- Robin updates the Northstart 2 DTS to use the generic IOMMU binding
- Scott renames the Broadcom Northstar 2 binding document to use a standard name
including the brcm vendor prefix
- Kamal adds the QSPI Device Tree node to the Northstar 2 SoC and updates the
Northstar 2 SVK reference board DTS file with it enabled.
- Rob adds the Device Tree node for the Broadcom PDC (mailbox) hardware to the
Northstar 2 SoC
- Jon enables the SDIO1 block and adds proper PCIe PHYs Device Tree nodes to the
Northstar 2 SoC
- Ray adds required properties NAND controller properties to make NAND work on
the Northstar 2 SVK board, this was submitted as a 4.9 fixes and is included
here to resolve DTS file merges
- Andrea removes an incorrect power LED from the Raspberry Pi 3 DTS
- Andreas fixes the compatible string for the BCM2837 (Raspberry Pi 3)
- Eric defines standard pinctrl groups in the BCM2835 GPIO node
- Gerd adds definitions for the pinctrl groups and updates the PWM, I2C and SDHCI nodes
to use their appropriate pinctrl functions
- Linus adds names for the Raspberry Pi GPIO lines based on the datasheet
- Martin adds the DT binding and nodes for the Raspberry Pi firmware thermal block
- Stefan fixes a few typos with respect to the BCM2835 mailbox binding example and
Device Tree nodes he also uses the proper DTSI file to define the USB host mode
for the USB Device Tree nodes
* tag 'arm-soc/for-4.10/devicetree-arm64' of http://github.com/Broadcom/stblinux: (23 commits)
arm64: dts: NS2: Add PCI PHYs
arm64: dts: NS2: enable sdio1
ARM64: dts: bcm2837-rpi-3-b: remove incorrect pwr LED
ARM64: bcm2835: dts: add thermal node to device-tree of bcm2837
ARM: bcm2835: Add names for the Raspberry Pi GPIO lines
ARM: bcm2835: dts: add thermal node to device-tree of bcm283x
dt: bindings: add thermal device driver for bcm2835
arm64: dts: Add Broadcom Northstar2 device tree entries for PDC driver.
ARM: dts: bcm283x: fix typo in mailbox address
DT: binding: bcm2835-mbox: fix address typo in example
ARM64: dts: bcm2835: Fix bcm2837 compatible string
arm64: dts: Update Broadcom NS2 to generic IOMMU binding
arm64: dts: Updated NAND DT properties for NS2 SVK
arm64: dts: rename ns2.txt to brcm,ns2.txt
ARM64: dts: Add QSPI Device Tree node for NS2
ARM64: dts: bcm283x: Use dtsi for USB host mode
ARM: dts: bcm283x: drop alt3 from &gpio
ARM: dts: bcm283x: add pinctrl group to &sdhci, drop pins from &gpio
ARM: dts: bcm283x: add pinctrl group to &i2c1, drop pins from &gpio
ARM: dts: bcm283x: add pinctrl group to &i2c0, drop pins from &gpio
...
This adds initial support for Tegra186, the P3310 processor module as
well as the P2771 development board. Not much is functional, but there
is enough to boot to an initial ramdisk with debug serial output.
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Merge tag 'tegra-for-4.10-arm64-dt-numeric-ids' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/dt64
Pull "arm64: tegra: Device tree changes for v4.10-rc1" from Thierry Reding:
This adds initial support for Tegra186, the P3310 processor module as
well as the P2771 development board. Not much is functional, but there
is enough to boot to an initial ramdisk with debug serial output.
* tag 'tegra-for-4.10-arm64-dt-numeric-ids' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
arm64: tegra: Add NVIDIA P2771 board support
arm64: tegra: Enable PSCI on P3310
arm64: tegra: Add NVIDIA P3310 processor module support
arm64: tegra: Add GPIO controllers on Tegra186
arm64: tegra: Add SDHCI controllers on Tegra186
arm64: tegra: Add I2C controllers on Tegra186
arm64: tegra: Add serial ports on Tegra186
arm64: tegra: Add CPU nodes for Tegra186
arm64: tegra: Add Tegra186 support
Two branches were incorrectly sent without having the necessary
header file changes. Rather than back those out now, I'm replacing
the symbolic names for the clks and resets with the numeric
values to get 'make allmodconfig dtbs' back to work.
After the header file changes are merged, we can revert this
patch.
Fixes: 6bc37fa ("arm64: dts: add Allwinner A64 SoC .dtsi")
Fixes: 50784e6 ("dts: arm64: db820c: add pmic pins specific dts file")
Acked-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Fix DTC warning on Armada 37xx and 7K/8K
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Merge tag 'mvebu-dt64-4.10-2' of git://git.infradead.org/linux-mvebu into next/dt64
Pull "mvebu dt64 for 4.10 (part 2)" from Gregory CLEMENT:
Fix DTC warning on Armada 37xx and 7K/8K
* tag 'mvebu-dt64-4.10-2' of git://git.infradead.org/linux-mvebu:
ARM64: dts: marvell: Fixup memory DT warning for Armada 37xx
arm64: dts: marvell: Fixup config-space DT warning For Armada 7K/8K
arm64: dts: marvell: Fixup internal-regs DT warning for Armada 37xx
Add PCIe support to the ARTPEC-6 SoC. This uses the existing
pcie-artpec6 driver.
So, all that is needed is device tree entries in the DTS.
Signed-off-by: Niklas Cassel <niklas.cassel@axis.com>
Signed-off-by: Jesper Nilsson <jespern@axis.com>
other fixes.
In order to get the thermal node that we're adjusting the compatible
string on, we have to merge in the bcm2835-dt-next branch.
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Merge tag 'bcm2835-dt-64-next-2016-11-18' into devicetree-arm64/next
This pull request brings thermal support to the BCM2837 DT, and a few
other fixes.
In order to get the thermal node that we're adjusting the compatible
string on, we have to merge in the bcm2835-dt-next branch.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
PCI PHYs are missing from the Northstar2 DT entries for the 2 PCI buses.
Add them so that PCI devices can be discovered.
Signed-off-by: Jon Mason <jon.mason@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Enable sdio1 in the Northstar2 SVK device tree file
Signed-off-by: Jon Mason <jon.mason@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
The NVIDIA P2771 is composed of a P3310 processor module that connects
to the P2597 I/O board. It comes with a 1200x1920 MIPI DSI panel that is
connected via the P2597's display connector and has several connectors
such as HDMI, USB 3.0, PCIe and ethernet.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The P3310 processor module comes ships with a firmware that implements
PSCI 1.0. Enable and use it to bring up all CPUs.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The NVIDIA P3310 is a processor module used in several reference designs
that features a Tegra186 SoC, 8 GiB of LPDDR4 RAM, 32 GiB eMMC and other
essentials such as ethernet, WiFi and a PMIC. It is typically connected
to an I/O board (such as the P2597) that provides the connecters needed
to hook it up to the outside world.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Tegra186 has two GPIO controllers that are no longer compatible with the
controller found on earlier generations. One of these controllers exists
in an always-on partition of the SoC whereas the other can be clock- and
powergated.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Tegra186 has a total of four SDHCI controllers that each support SD 4.2
(up to UHS-I speed), SDIO 4.1 (up to UHS-I speed), eSD 2.1, eMMC 5.1 and
SDHOST 4.1 (up to UHS-I speed).
Signed-off-by: Thierry Reding <treding@nvidia.com>
Tegra186 has a total of nine I2C controllers that are compatible with
the I2C controllers introduced in Tegra114. Two of these controllers
share pads with two DPAUX controllers (for AUX transactions).
Signed-off-by: Thierry Reding <treding@nvidia.com>
The initial patch only added UARTA, but there's no reason we shouldn't
be adding all of them. While at it, also specify the missing clocks and
resets for UARTA.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Tegra186 has six CPUs: two CPUs are second generation Denver CPUs that
support ARMv8 and four CPUs are Cortex-A57 CPUs.
Signed-off-by: Thierry Reding <treding@nvidia.com>
This adds the initial support of Tegra186 SoC. It provides enough to
enable the serial console and boot from an initial ramdisk.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
[treding@nvidia.com: remove leading 0 from unit-addresses]
[treding@nvidia.com: remove unused nvidia,bpmp property]
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add a device node for the Product Register, which provides SoC product
and revision information.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add a device node for the Product Register, which provides SoC product
and revision information.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This changes SDHI0 pin names for H3ULCB board
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This supports SDHI2 for H3ULCB onboard eMMC
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This supports SDHI2 for M3ULCB onboard eMMC
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This supports SDHI0 on M3ULCB board SD card slot
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This supports watchdog timer for M3ULCB board
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This enables EXTALR clock that can be used for the watchdog.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This supports GPIO keys on M3ULCB board
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This supports GPIO leds on M3ULCB board
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This enables the external crystal for the SCIF_CLK and its pinctrl, to
be used by the Baud Rate Generator for External Clock (BRG) on (H)SCIF.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add the initial device tree for the R8A7796 SoC based M3ULCB low cost
board (R-Car Starter Kit Pro)
This commit supports the following peripherals:
- SCIF (console)
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add M3ULCB Device tree bindings Documentation, listing it as a supported
board.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This updates H3ULCB device tree header with official board name
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This updates H3ULCB Device tree bindings Documentation with
official board name
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Fix invalid GIC interrupt flags - type IRQ_TYPE_NONE is not allowed for GIC
interrupts. Although this was working but with error messages like:
genirq: Setting trigger mode 0 for irq 16 failed
Use level high interrupt instead of type none. The choice of level high was
rather an arbitrary decision hoping it will work on each platform. Tests shown
no issues so far.
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Merge tag 'samsung-dt64-gic-flags-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/dt64
Topic branch with DT arm64 changes for v4.10.
Fix invalid GIC interrupt flags - type IRQ_TYPE_NONE is not allowed for GIC
interrupts. Although this was working but with error messages like:
genirq: Setting trigger mode 0 for irq 16 failed
Use level high interrupt instead of type none. The choice of level high was
rather an arbitrary decision hoping it will work on each platform. Tests shown
no issues so far.
* tag 'samsung-dt64-gic-flags-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
arm64: dts: exynos: Use human-friendly symbols for interrupt properties in exynos7
arm64: dts: exynos: Fix invalid GIC interrupt flags in exynos7
Signed-off-by: Olof Johansson <olof@lixom.net>
Adding the new "community" board for Armada 3700
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Merge tag 'mvebu-dt64-4.10-1' of git://git.infradead.org/linux-mvebu into next/dt64
mvebu dt64 for 4.10 (part 1)
Adding the new "community" board for Armada 3700
* tag 'mvebu-dt64-4.10-1' of git://git.infradead.org/linux-mvebu:
arm64: dts: marvell: Add definition for the Globalscale Marvell ESPRESSOBin Board
Signed-off-by: Olof Johansson <olof@lixom.net>
Support for the Allwinner A64, their first armv8 SoC.
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Merge tag 'sunxi-dt64-for-4.10' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into next/dt64
Allwinner arm64 DT changes for 4.10
Support for the Allwinner A64, their first armv8 SoC.
* tag 'sunxi-dt64-for-4.10' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux:
arm64: dts: add Pine64 support
Documentation: devicetree: add vendor prefix for Pine64
arm64: dts: add Allwinner A64 SoC .dtsi
Signed-off-by: Olof Johansson <olof@lixom.net>
- Correct the hardware pin number of the usb node on the Hip06
- Add the Hisilicon Hip07 D05 board dts binding
- Add the initial dts for the Hip07 D05 board
- Fix the warning for the node without reg propery on the Hip06
- Fix the sas am max transmissions quirk property on the Hip06
- Disable the sas0 and sas2 on D03 board
- Add refclk node for SAS on the Hip06
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Merge tag 'hisi-arm64-dt-4.10' of git://github.com/hisilicon/linux-hisi into next/dt64
ARM64: DT: Hisilicon SoC DT updates for 4.10
- Correct the hardware pin number of the usb node on the Hip06
- Add the Hisilicon Hip07 D05 board dts binding
- Add the initial dts for the Hip07 D05 board
- Fix the warning for the node without reg propery on the Hip06
- Fix the sas am max transmissions quirk property on the Hip06
- Disable the sas0 and sas2 on D03 board
- Add refclk node for SAS on the Hip06
* tag 'hisi-arm64-dt-4.10' of git://github.com/hisilicon/linux-hisi:
arm64: dts: hisi: add refclk node to hip06 dts files for SAS
arm64: dts: hisi: disable sas0 and sas2 for d03
arm64: dts: hisi: fix hip06 sas am-max-trans quirk
arm64: dts: hip06: Fix no reg property warning
arm64: dts: hisilicon: Add initial dts for Hip07 D05 board
Documentation: arm64: Add Hisilicon Hip07 D05 dts binding
arm64: dts: hip06: Correct hardware pin number of usb node
Signed-off-by: Olof Johansson <olof@lixom.net>
- Enable Thermal Monitoring Unit (TMU) for thermal management on
LS1043A and LS2080A.
- Add support for LS1046A SoC, which has similar peripherals as
LS1043A but integrates 4 A72 cores.
- Add two LS1046A based board support: LS1046A-QDS and LS1046A-RDB.
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Merge tag 'imx-dt64-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt64
Freescale arm64 device tree updates for 4.10:
- Enable Thermal Monitoring Unit (TMU) for thermal management on
LS1043A and LS2080A.
- Add support for LS1046A SoC, which has similar peripherals as
LS1043A but integrates 4 A72 cores.
- Add two LS1046A based board support: LS1046A-QDS and LS1046A-RDB.
* tag 'imx-dt64-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
arm64: dts: ls2080a: Add TMU device tree support for LS2080A
arm64: dts: ls1043a: Add TMU device tree support for LS1043A
arm64: dts: add LS1046A-QDS board support
Documentation: DT: Add entry for QorIQ LS1046A-QDS board
arm64: dts: add LS1046A-RDB board support
Documentation: DT: Add entry for QorIQ LS1046A-RDB board
arm64: dts: add QorIQ LS1046A SoC support
dt-bindings: ahci-fsl-qoriq: updated for SoC ls1046a
dt-bindings: qoriq-clock: add LS1043A/LS1046A/LS2080A compatible for clockgen
dt-bindings: i2c: adds two more nxp devices
dt-bindings: fsl: add LS1043A/LS1046A/LS2080A compatible for SCFG and DCFG
dt-bindings: fsl: Add LS1043A/LS1046A/LS2080A SoC compatible strings
Signed-off-by: Olof Johansson <olof@lixom.net>
* 'clk-qcom-8994' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
clk: qcom: Add support for msm8994 global clock controller
dt-bindings: qcom: clocks: Add msm8994 clock bindings
a fix for wrong i2c registers on rk3368 a new nvmem cell and
power-domain on rk3399 as well as moving mmc frequency
properties to the more generic max-frequency one.
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Merge tag 'v4.10-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt64
64bit devicetree changes including the px5 evaluation board
a fix for wrong i2c registers on rk3368 a new nvmem cell and
power-domain on rk3399 as well as moving mmc frequency
properties to the more generic max-frequency one.
* tag 'v4.10-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
arm64: dts: rockchip: replace to "max-frequency" instead of "clock-freq-min-max"
arm64: dts: rockchip: add cpu-id nvmem cell node for rk3399
arm64: dts: rockchip: add sdmmc support for px5-evb
arm64: dts: rockchip: Add more properties for emmc on px5-evb
arm64: dts: rockchip: Add PX5 Evaluation board
arm64: dts: rockchip: add powerdomain for typec on rk3399
arm64: dts: rockchip: fix i2c resource error of rk3368
Signed-off-by: Olof Johansson <olof@lixom.net>
SoC along with two boards. A lot of Samsung people contributed into this
but the final work and commits were done by Chanwoo Choi.
This means that for v4.10 we got:
1. Exynos5433 DTSI.
2. Two boards: TM2 and TM2E. These are (almost fully) working mobile phones.
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Merge tag 'samsung-dt64-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/dt64
Finally, I am really pleased to announce adding support for Exynos5433 ARMv8
SoC along with two boards. A lot of Samsung people contributed into this
but the final work and commits were done by Chanwoo Choi.
This means that for v4.10 we got:
1. Exynos5433 DTSI.
2. Two boards: TM2 and TM2E. These are (almost fully) working mobile phones.
* tag 'samsung-dt64-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
arm64: dts: exynos: Add dts file for Exynos5433-based TM2E board
arm64: dts: exynos: Add dts file for Exynos5433-based TM2 board
arm64: dts: exynos: Add dtsi files for Samsung Exynos5433 64bit SoC
Signed-off-by: Olof Johansson <olof@lixom.net>
- Switch CPU enable-method from spin-table to PSCI
- Add OPP tables to support generic cpufreq driver
- Misc fixes
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Merge tag 'uniphier-dt64-v4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier into next/dt64
UniPhier ARM64 SoC DT updates for v4.10
- Switch CPU enable-method from spin-table to PSCI
- Add OPP tables to support generic cpufreq driver
- Misc fixes
* tag 'uniphier-dt64-v4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier:
arm64: dts: uniphier: make compatible of syscon nodes SoC-specific
arm64: dts: uniphier: add CPU clocks and OPP tables for LD20 SoC
arm64: dts: uniphier: add CPU clock and OPP table for LD11 SoC
arm64: dts: uniphier: increase register region size of sysctrl node
arm64: dts: uniphier: switch over to PSCI enable method
Signed-off-by: Olof Johansson <olof@lixom.net>
