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Author SHA1 Message Date
Icenowy Zheng
37cabc74e5 clk: sunxi-ng: fix PRCM CCU ir clk parent 
The first parent of ir clk in PRCM CCU is wrongly written as "osc32K"
instead of "osc32k".

Change it to "osc32k".

Fixes: cdb8b80b60 ("clk: sunxi-ng: add support for PRCM CCUs")

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
 2017-04-10 09:04:23 +02:00
Icenowy Zheng
cdb8b80b60 clk: sunxi-ng: add support for PRCM CCUs 
SoCs after A31 has a clock controller module in the PRCM part.

Support the clock controller module on H3/5 and A64 now.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
 2017-04-04 17:43:52 +02:00