Commit graph

7 commits

Author SHA1 Message Date
Stephen Warren
6bb27d7349 ARM: delete struct sys_timer
Now that the only field in struct sys_timer is .init, delete the struct,
and replace the machine descriptor .timer field with the initialization
function itself.

This will enable moving timer drivers into drivers/clocksource without
having to place a public prototype of each struct sys_timer object into
include/linux; the intent is to create a single of_clocksource_init()
function that determines which timer driver to initialize by scanning
the device dtree, much like the proposed irqchip_init() at:
http://www.spinics.net/lists/arm-kernel/msg203686.html

Includes mach-omap2 fixes from Igor Grinberg.

Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-12-24 09:36:38 -07:00
Russell King
3921470527 ARM: restart: cns3xxx: use new restart hook
Hook these platforms restart code into the new restart hook rather
than using arch_reset().

Acked-by: Anton Vorontsov <cbouatmailru@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2012-01-05 12:57:09 +00:00
Anton Vorontsov
93e85d8e90 ARM: cns3xxx: Add support for L2 Cache Controller
CNS3xxx SOCs have L310-compatible cache controller, so let's use it.

With this patch benchmarking with 'gzip' shows that performance is
doubled, and I'm still able to boot full-fledged userland over NFS
(using PCIe NIC), so the support should be pretty robust.

p.s. While CNS3xxx reports that it has PL310, it still needs to wait
on cache line operations, so we should not select 'CACHE_PL310',
which is a micro-optimization that removes these waits for v7 CPUs.
Someday we'd better rename CACHE_PL310 Kconfig option into
NO_CACHE_WAIT or something less ambiguous.

Signed-off-by: Anton Vorontsov <avorontsov@mvista.com>
2011-07-07 18:48:38 +04:00
Russell King
404a02cbd2 Merge branch 'devel-stable' into devel
Conflicts:
	arch/arm/mach-pxa/clock.c
	arch/arm/mach-pxa/clock.h
2011-01-06 22:33:32 +00:00
Russell King
ff2e27ae0b ARM: GIC: consolidate gic_cpu_base_addr to common GIC code
Every architecture using the GIC has a gic_cpu_base_addr pointer for
GIC 0 for their entry assembly code to use to decode the cause of the
current interrupt.  Move this into the common GIC code.

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-12-14 19:21:42 +00:00
Mac Lin
38e64ba0f1 ARM: cns3xxx: Add new and export the old power management functions
This patch adds cns3xxx_pwr_clk_dis, and exports these power management
functions that may be used by many other device drivers on CNS3XXX.

Signed-off-by: Mac Lin <mkl0301@gmail.com>
Signed-off-by: Anton Vorontsov <cbouatmailru@gmail.com>
2010-11-26 21:10:50 +03:00
Anton Vorontsov
d94f944e10 ARM: cns3xxx: Add basic support for Cavium Networks CNS3xxx processors
This patch adds very basic support for ECONA CNS3xxx ARM11 MPcore
(ARMv6) dual-core processors.

Note that SMP is not yet supported, as well as many peripheral
devices. Support for these features will be added later.

Signed-off-by: Anton Vorontsov <avorontsov@mvista.com>
2010-05-02 21:55:46 +04:00