a5c149c8a0
These headers are used by Linux but are maintained upstream. This change incorporates a few minor fixes to these headers, including a new sim_print() function, cleaner support for the sim_syscall() API, and a sim_query_cpu_speed() method. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
505 lines
15 KiB
C
505 lines
15 KiB
C
/*
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* Copyright 2010 Tilera Corporation. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for
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* more details.
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*/
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/**
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* @file
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*
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* Some low-level simulator definitions.
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*/
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#ifndef __ARCH_SIM_DEF_H__
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#define __ARCH_SIM_DEF_H__
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/**
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* Internal: the low bits of the SIM_CONTROL_* SPR values specify
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* the operation to perform, and the remaining bits are
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* an operation-specific parameter (often unused).
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*/
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#define _SIM_CONTROL_OPERATOR_BITS 8
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/*
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* Values which can be written to SPR_SIM_CONTROL.
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*/
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/** If written to SPR_SIM_CONTROL, stops profiling. */
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#define SIM_CONTROL_PROFILER_DISABLE 0
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/** If written to SPR_SIM_CONTROL, starts profiling. */
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#define SIM_CONTROL_PROFILER_ENABLE 1
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/** If written to SPR_SIM_CONTROL, clears profiling counters. */
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#define SIM_CONTROL_PROFILER_CLEAR 2
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/** If written to SPR_SIM_CONTROL, checkpoints the simulator. */
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#define SIM_CONTROL_CHECKPOINT 3
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/**
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* If written to SPR_SIM_CONTROL, combined with a mask (shifted by 8),
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* sets the tracing mask to the given mask. See "sim_set_tracing()".
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*/
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#define SIM_CONTROL_SET_TRACING 4
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/**
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* If written to SPR_SIM_CONTROL, combined with a mask (shifted by 8),
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* dumps the requested items of machine state to the log.
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*/
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#define SIM_CONTROL_DUMP 5
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/** If written to SPR_SIM_CONTROL, clears chip-level profiling counters. */
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#define SIM_CONTROL_PROFILER_CHIP_CLEAR 6
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/** If written to SPR_SIM_CONTROL, disables chip-level profiling. */
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#define SIM_CONTROL_PROFILER_CHIP_DISABLE 7
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/** If written to SPR_SIM_CONTROL, enables chip-level profiling. */
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#define SIM_CONTROL_PROFILER_CHIP_ENABLE 8
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/** If written to SPR_SIM_CONTROL, enables chip-level functional mode */
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#define SIM_CONTROL_ENABLE_FUNCTIONAL 9
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/** If written to SPR_SIM_CONTROL, disables chip-level functional mode. */
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#define SIM_CONTROL_DISABLE_FUNCTIONAL 10
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/**
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* If written to SPR_SIM_CONTROL, enables chip-level functional mode.
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* All tiles must perform this write for functional mode to be enabled.
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* Ignored in naked boot mode unless --functional is specified.
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* WARNING: Only the hypervisor startup code should use this!
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*/
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#define SIM_CONTROL_ENABLE_FUNCTIONAL_BARRIER 11
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/**
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* If written to SPR_SIM_CONTROL, combined with a character (shifted by 8),
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* writes a string directly to the simulator output. Written to once for
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* each character in the string, plus a final NUL. Instead of NUL,
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* you can also use "SIM_PUTC_FLUSH_STRING" or "SIM_PUTC_FLUSH_BINARY".
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*/
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/* ISSUE: Document the meaning of "newline", and the handling of NUL. */
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#define SIM_CONTROL_PUTC 12
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/**
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* If written to SPR_SIM_CONTROL, clears the --grind-coherence state for
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* this core. This is intended to be used before a loop that will
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* invalidate the cache by loading new data and evicting all current data.
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* Generally speaking, this API should only be used by system code.
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*/
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#define SIM_CONTROL_GRINDER_CLEAR 13
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/** If written to SPR_SIM_CONTROL, shuts down the simulator. */
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#define SIM_CONTROL_SHUTDOWN 14
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/**
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* If written to SPR_SIM_CONTROL, combined with a pid (shifted by 8),
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* indicates that a fork syscall just created the given process.
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*/
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#define SIM_CONTROL_OS_FORK 15
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/**
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* If written to SPR_SIM_CONTROL, combined with a pid (shifted by 8),
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* indicates that an exit syscall was just executed by the given process.
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*/
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#define SIM_CONTROL_OS_EXIT 16
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/**
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* If written to SPR_SIM_CONTROL, combined with a pid (shifted by 8),
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* indicates that the OS just switched to the given process.
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*/
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#define SIM_CONTROL_OS_SWITCH 17
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/**
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* If written to SPR_SIM_CONTROL, combined with a character (shifted by 8),
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* indicates that an exec syscall was just executed. Written to once for
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* each character in the executable name, plus a final NUL.
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*/
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#define SIM_CONTROL_OS_EXEC 18
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/**
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* If written to SPR_SIM_CONTROL, combined with a character (shifted by 8),
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* indicates that an interpreter (PT_INTERP) was loaded. Written to once
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* for each character in "ADDR:PATH", plus a final NUL, where "ADDR" is a
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* hex load address starting with "0x", and "PATH" is the executable name.
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*/
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#define SIM_CONTROL_OS_INTERP 19
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/**
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* If written to SPR_SIM_CONTROL, combined with a character (shifted by 8),
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* indicates that a dll was loaded. Written to once for each character
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* in "ADDR:PATH", plus a final NUL, where "ADDR" is a hexadecimal load
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* address starting with "0x", and "PATH" is the executable name.
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*/
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#define SIM_CONTROL_DLOPEN 20
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/**
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* If written to SPR_SIM_CONTROL, combined with a character (shifted by 8),
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* indicates that a dll was unloaded. Written to once for each character
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* in "ADDR", plus a final NUL, where "ADDR" is a hexadecimal load
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* address starting with "0x".
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*/
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#define SIM_CONTROL_DLCLOSE 21
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/**
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* If written to SPR_SIM_CONTROL, combined with a flag (shifted by 8),
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* indicates whether to allow data reads to remotely-cached
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* dirty cache lines to be cached locally without grinder warnings or
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* assertions (used by Linux kernel fast memcpy).
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*/
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#define SIM_CONTROL_ALLOW_MULTIPLE_CACHING 22
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/** If written to SPR_SIM_CONTROL, enables memory tracing. */
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#define SIM_CONTROL_ENABLE_MEM_LOGGING 23
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/** If written to SPR_SIM_CONTROL, disables memory tracing. */
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#define SIM_CONTROL_DISABLE_MEM_LOGGING 24
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/**
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* If written to SPR_SIM_CONTROL, changes the shaping parameters of one of
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* the gbe or xgbe shims. Must specify the shim id, the type, the units, and
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* the rate, as defined in SIM_SHAPING_SPR_ARG.
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*/
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#define SIM_CONTROL_SHAPING 25
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/**
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* If written to SPR_SIM_CONTROL, combined with character (shifted by 8),
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* requests that a simulator command be executed. Written to once for each
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* character in the command, plus a final NUL.
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*/
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#define SIM_CONTROL_COMMAND 26
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/**
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* If written to SPR_SIM_CONTROL, indicates that the simulated system
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* is panicking, to allow debugging via --debug-on-panic.
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*/
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#define SIM_CONTROL_PANIC 27
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/**
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* If written to SPR_SIM_CONTROL, triggers a simulator syscall.
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* See "sim_syscall()" for more info.
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*/
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#define SIM_CONTROL_SYSCALL 32
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/**
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* If written to SPR_SIM_CONTROL, combined with a pid (shifted by 8),
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* provides the pid that subsequent SIM_CONTROL_OS_FORK writes should
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* use as the pid, rather than the default previous SIM_CONTROL_OS_SWITCH.
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*/
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#define SIM_CONTROL_OS_FORK_PARENT 33
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/**
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* If written to SPR_SIM_CONTROL, combined with a mPIPE shim number
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* (shifted by 8), clears the pending magic data section. The cleared
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* pending magic data section and any subsequently appended magic bytes
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* will only take effect when the classifier blast programmer is run.
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*/
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#define SIM_CONTROL_CLEAR_MPIPE_MAGIC_BYTES 34
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/**
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* If written to SPR_SIM_CONTROL, combined with a mPIPE shim number
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* (shifted by 8) and a byte of data (shifted by 16), appends that byte
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* to the shim's pending magic data section. The pending magic data
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* section takes effect when the classifier blast programmer is run.
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*/
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#define SIM_CONTROL_APPEND_MPIPE_MAGIC_BYTE 35
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/**
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* If written to SPR_SIM_CONTROL, combined with a mPIPE shim number
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* (shifted by 8), an enable=1/disable=0 bit (shifted by 16), and a
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* mask of links (shifted by 32), enable or disable the corresponding
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* mPIPE links.
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*/
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#define SIM_CONTROL_ENABLE_MPIPE_LINK_MAGIC_BYTE 36
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/*
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* Syscall numbers for use with "sim_syscall()".
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*/
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/** Syscall number for sim_add_watchpoint(). */
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#define SIM_SYSCALL_ADD_WATCHPOINT 2
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/** Syscall number for sim_remove_watchpoint(). */
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#define SIM_SYSCALL_REMOVE_WATCHPOINT 3
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/** Syscall number for sim_query_watchpoint(). */
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#define SIM_SYSCALL_QUERY_WATCHPOINT 4
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/**
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* Syscall number that asserts that the cache lines whose 64-bit PA
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* is passed as the second argument to sim_syscall(), and over a
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* range passed as the third argument, are no longer in cache.
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* The simulator raises an error if this is not the case.
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*/
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#define SIM_SYSCALL_VALIDATE_LINES_EVICTED 5
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/** Syscall number for sim_query_cpu_speed(). */
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#define SIM_SYSCALL_QUERY_CPU_SPEED 6
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/*
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* Bit masks which can be shifted by 8, combined with
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* SIM_CONTROL_SET_TRACING, and written to SPR_SIM_CONTROL.
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*/
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/**
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* @addtogroup arch_sim
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* @{
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*/
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/** Enable --trace-cycle when passed to simulator_set_tracing(). */
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#define SIM_TRACE_CYCLES 0x01
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/** Enable --trace-router when passed to simulator_set_tracing(). */
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#define SIM_TRACE_ROUTER 0x02
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/** Enable --trace-register-writes when passed to simulator_set_tracing(). */
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#define SIM_TRACE_REGISTER_WRITES 0x04
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/** Enable --trace-disasm when passed to simulator_set_tracing(). */
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#define SIM_TRACE_DISASM 0x08
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/** Enable --trace-stall-info when passed to simulator_set_tracing(). */
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#define SIM_TRACE_STALL_INFO 0x10
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/** Enable --trace-memory-controller when passed to simulator_set_tracing(). */
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#define SIM_TRACE_MEMORY_CONTROLLER 0x20
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/** Enable --trace-l2 when passed to simulator_set_tracing(). */
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#define SIM_TRACE_L2_CACHE 0x40
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/** Enable --trace-lines when passed to simulator_set_tracing(). */
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#define SIM_TRACE_LINES 0x80
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/** Turn off all tracing when passed to simulator_set_tracing(). */
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#define SIM_TRACE_NONE 0
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/** Turn on all tracing when passed to simulator_set_tracing(). */
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#define SIM_TRACE_ALL (-1)
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/** @} */
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/** Computes the value to write to SPR_SIM_CONTROL to set tracing flags. */
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#define SIM_TRACE_SPR_ARG(mask) \
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(SIM_CONTROL_SET_TRACING | ((mask) << _SIM_CONTROL_OPERATOR_BITS))
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/*
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* Bit masks which can be shifted by 8, combined with
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* SIM_CONTROL_DUMP, and written to SPR_SIM_CONTROL.
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*/
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/**
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* @addtogroup arch_sim
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* @{
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*/
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/** Dump the general-purpose registers. */
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#define SIM_DUMP_REGS 0x001
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/** Dump the SPRs. */
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#define SIM_DUMP_SPRS 0x002
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/** Dump the ITLB. */
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#define SIM_DUMP_ITLB 0x004
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/** Dump the DTLB. */
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#define SIM_DUMP_DTLB 0x008
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/** Dump the L1 I-cache. */
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#define SIM_DUMP_L1I 0x010
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/** Dump the L1 D-cache. */
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#define SIM_DUMP_L1D 0x020
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/** Dump the L2 cache. */
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#define SIM_DUMP_L2 0x040
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/** Dump the switch registers. */
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#define SIM_DUMP_SNREGS 0x080
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/** Dump the switch ITLB. */
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#define SIM_DUMP_SNITLB 0x100
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/** Dump the switch L1 I-cache. */
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#define SIM_DUMP_SNL1I 0x200
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/** Dump the current backtrace. */
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#define SIM_DUMP_BACKTRACE 0x400
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/** Only dump valid lines in caches. */
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#define SIM_DUMP_VALID_LINES 0x800
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/** Dump everything that is dumpable. */
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#define SIM_DUMP_ALL (-1 & ~SIM_DUMP_VALID_LINES)
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/** @} */
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/** Computes the value to write to SPR_SIM_CONTROL to dump machine state. */
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#define SIM_DUMP_SPR_ARG(mask) \
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(SIM_CONTROL_DUMP | ((mask) << _SIM_CONTROL_OPERATOR_BITS))
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/*
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* Bit masks which can be shifted by 8, combined with
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* SIM_CONTROL_PROFILER_CHIP_xxx, and written to SPR_SIM_CONTROL.
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*/
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/**
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* @addtogroup arch_sim
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* @{
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*/
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/** Use with with SIM_PROFILER_CHIP_xxx to control the memory controllers. */
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#define SIM_CHIP_MEMCTL 0x001
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/** Use with with SIM_PROFILER_CHIP_xxx to control the XAUI interface. */
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#define SIM_CHIP_XAUI 0x002
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/** Use with with SIM_PROFILER_CHIP_xxx to control the PCIe interface. */
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#define SIM_CHIP_PCIE 0x004
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/** Use with with SIM_PROFILER_CHIP_xxx to control the MPIPE interface. */
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#define SIM_CHIP_MPIPE 0x008
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/** Use with with SIM_PROFILER_CHIP_xxx to control the TRIO interface. */
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#define SIM_CHIP_TRIO 0x010
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/** Reference all chip devices. */
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#define SIM_CHIP_ALL (-1)
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/** @} */
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/** Computes the value to write to SPR_SIM_CONTROL to clear chip statistics. */
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#define SIM_PROFILER_CHIP_CLEAR_SPR_ARG(mask) \
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(SIM_CONTROL_PROFILER_CHIP_CLEAR | ((mask) << _SIM_CONTROL_OPERATOR_BITS))
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/** Computes the value to write to SPR_SIM_CONTROL to disable chip statistics.*/
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#define SIM_PROFILER_CHIP_DISABLE_SPR_ARG(mask) \
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(SIM_CONTROL_PROFILER_CHIP_DISABLE | ((mask) << _SIM_CONTROL_OPERATOR_BITS))
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/** Computes the value to write to SPR_SIM_CONTROL to enable chip statistics. */
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#define SIM_PROFILER_CHIP_ENABLE_SPR_ARG(mask) \
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(SIM_CONTROL_PROFILER_CHIP_ENABLE | ((mask) << _SIM_CONTROL_OPERATOR_BITS))
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/* Shim bitrate controls. */
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/** The number of bits used to store the shim id. */
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#define SIM_CONTROL_SHAPING_SHIM_ID_BITS 3
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/**
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* @addtogroup arch_sim
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* @{
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*/
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/** Change the gbe 0 bitrate. */
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#define SIM_CONTROL_SHAPING_GBE_0 0x0
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/** Change the gbe 1 bitrate. */
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#define SIM_CONTROL_SHAPING_GBE_1 0x1
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/** Change the gbe 2 bitrate. */
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#define SIM_CONTROL_SHAPING_GBE_2 0x2
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/** Change the gbe 3 bitrate. */
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#define SIM_CONTROL_SHAPING_GBE_3 0x3
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/** Change the xgbe 0 bitrate. */
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#define SIM_CONTROL_SHAPING_XGBE_0 0x4
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/** Change the xgbe 1 bitrate. */
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#define SIM_CONTROL_SHAPING_XGBE_1 0x5
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/** The type of shaping to do. */
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#define SIM_CONTROL_SHAPING_TYPE_BITS 2
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/** Control the multiplier. */
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#define SIM_CONTROL_SHAPING_MULTIPLIER 0
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/** Control the PPS. */
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#define SIM_CONTROL_SHAPING_PPS 1
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/** Control the BPS. */
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#define SIM_CONTROL_SHAPING_BPS 2
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/** The number of bits for the units for the shaping parameter. */
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#define SIM_CONTROL_SHAPING_UNITS_BITS 2
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/** Provide a number in single units. */
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#define SIM_CONTROL_SHAPING_UNITS_SINGLE 0
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/** Provide a number in kilo units. */
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#define SIM_CONTROL_SHAPING_UNITS_KILO 1
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/** Provide a number in mega units. */
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#define SIM_CONTROL_SHAPING_UNITS_MEGA 2
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/** Provide a number in giga units. */
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#define SIM_CONTROL_SHAPING_UNITS_GIGA 3
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/** @} */
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/** How many bits are available for the rate. */
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#define SIM_CONTROL_SHAPING_RATE_BITS \
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(32 - (_SIM_CONTROL_OPERATOR_BITS + \
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SIM_CONTROL_SHAPING_SHIM_ID_BITS + \
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SIM_CONTROL_SHAPING_TYPE_BITS + \
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SIM_CONTROL_SHAPING_UNITS_BITS))
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/** Computes the value to write to SPR_SIM_CONTROL to change a bitrate. */
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#define SIM_SHAPING_SPR_ARG(shim, type, units, rate) \
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(SIM_CONTROL_SHAPING | \
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((shim) | \
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((type) << (SIM_CONTROL_SHAPING_SHIM_ID_BITS)) | \
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((units) << (SIM_CONTROL_SHAPING_SHIM_ID_BITS + \
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SIM_CONTROL_SHAPING_TYPE_BITS)) | \
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((rate) << (SIM_CONTROL_SHAPING_SHIM_ID_BITS + \
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SIM_CONTROL_SHAPING_TYPE_BITS + \
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SIM_CONTROL_SHAPING_UNITS_BITS))) << _SIM_CONTROL_OPERATOR_BITS)
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/*
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* Values returned when reading SPR_SIM_CONTROL.
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* ISSUE: These names should share a longer common prefix.
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*/
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/**
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* When reading SPR_SIM_CONTROL, the mask of simulator tracing bits
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* (SIM_TRACE_xxx values).
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*/
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#define SIM_TRACE_FLAG_MASK 0xFFFF
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/** When reading SPR_SIM_CONTROL, the mask for whether profiling is enabled. */
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#define SIM_PROFILER_ENABLED_MASK 0x10000
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/*
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* Special arguments for "SIM_CONTROL_PUTC".
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*/
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/**
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* Flag value for forcing a PUTC string-flush, including
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* coordinate/cycle prefix and newline.
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*/
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#define SIM_PUTC_FLUSH_STRING 0x100
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/**
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* Flag value for forcing a PUTC binary-data-flush, which skips the
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* prefix and does not append a newline.
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*/
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#define SIM_PUTC_FLUSH_BINARY 0x101
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#endif /* __ARCH_SIM_DEF_H__ */
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