0513fe9e5b
If the device that is to be shared with a guest is a level device and the IRQ is shared with the initial domain we need to take actions. Mainly we install a dummy IRQ handler that will ACK on the interrupt line so as to not have the initial domain disable the interrupt line. This dummy IRQ handler is not enabled when the device MSI/MSI-X lines are set, nor for edge interrupts. And also not for level interrupts that are not shared amongst devices. Lastly, if the user passes to the guest all of the PCI devices on the shared line the we won't install the dummy handler either. There is also SysFS instrumentation to check its state and turn IRQ ACKing on/off if necessary. Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
385 lines
8.6 KiB
C
385 lines
8.6 KiB
C
/*
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* PCI Backend - Handles the virtual fields in the configuration space headers.
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*
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* Author: Ryan Wilson <hap9@epoch.ncsc.mil>
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*/
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include "pciback.h"
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#include "conf_space.h"
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struct pci_bar_info {
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u32 val;
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u32 len_val;
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int which;
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};
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#define is_enable_cmd(value) ((value)&(PCI_COMMAND_MEMORY|PCI_COMMAND_IO))
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#define is_master_cmd(value) ((value)&PCI_COMMAND_MASTER)
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static int command_read(struct pci_dev *dev, int offset, u16 *value, void *data)
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{
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int i;
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int ret;
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ret = pciback_read_config_word(dev, offset, value, data);
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if (!atomic_read(&dev->enable_cnt))
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return ret;
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for (i = 0; i < PCI_ROM_RESOURCE; i++) {
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if (dev->resource[i].flags & IORESOURCE_IO)
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*value |= PCI_COMMAND_IO;
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if (dev->resource[i].flags & IORESOURCE_MEM)
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*value |= PCI_COMMAND_MEMORY;
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}
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return ret;
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}
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static int command_write(struct pci_dev *dev, int offset, u16 value, void *data)
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{
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struct pciback_dev_data *dev_data;
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int err;
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dev_data = pci_get_drvdata(dev);
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if (!pci_is_enabled(dev) && is_enable_cmd(value)) {
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if (unlikely(verbose_request))
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printk(KERN_DEBUG "pciback: %s: enable\n",
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pci_name(dev));
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err = pci_enable_device(dev);
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if (err)
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return err;
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if (dev_data)
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dev_data->enable_intx = 1;
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} else if (pci_is_enabled(dev) && !is_enable_cmd(value)) {
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if (unlikely(verbose_request))
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printk(KERN_DEBUG "pciback: %s: disable\n",
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pci_name(dev));
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pci_disable_device(dev);
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if (dev_data)
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dev_data->enable_intx = 0;
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}
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if (!dev->is_busmaster && is_master_cmd(value)) {
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if (unlikely(verbose_request))
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printk(KERN_DEBUG "pciback: %s: set bus master\n",
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pci_name(dev));
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pci_set_master(dev);
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}
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if (value & PCI_COMMAND_INVALIDATE) {
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if (unlikely(verbose_request))
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printk(KERN_DEBUG
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"pciback: %s: enable memory-write-invalidate\n",
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pci_name(dev));
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err = pci_set_mwi(dev);
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if (err) {
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printk(KERN_WARNING
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"pciback: %s: cannot enable "
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"memory-write-invalidate (%d)\n",
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pci_name(dev), err);
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value &= ~PCI_COMMAND_INVALIDATE;
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}
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}
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return pci_write_config_word(dev, offset, value);
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}
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static int rom_write(struct pci_dev *dev, int offset, u32 value, void *data)
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{
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struct pci_bar_info *bar = data;
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if (unlikely(!bar)) {
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printk(KERN_WARNING "pciback: driver data not found for %s\n",
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pci_name(dev));
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return XEN_PCI_ERR_op_failed;
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}
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/* A write to obtain the length must happen as a 32-bit write.
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* This does not (yet) support writing individual bytes
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*/
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if (value == ~PCI_ROM_ADDRESS_ENABLE)
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bar->which = 1;
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else {
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u32 tmpval;
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pci_read_config_dword(dev, offset, &tmpval);
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if (tmpval != bar->val && value == bar->val) {
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/* Allow restoration of bar value. */
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pci_write_config_dword(dev, offset, bar->val);
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}
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bar->which = 0;
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}
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/* Do we need to support enabling/disabling the rom address here? */
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return 0;
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}
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/* For the BARs, only allow writes which write ~0 or
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* the correct resource information
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* (Needed for when the driver probes the resource usage)
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*/
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static int bar_write(struct pci_dev *dev, int offset, u32 value, void *data)
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{
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struct pci_bar_info *bar = data;
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if (unlikely(!bar)) {
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printk(KERN_WARNING "pciback: driver data not found for %s\n",
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pci_name(dev));
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return XEN_PCI_ERR_op_failed;
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}
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/* A write to obtain the length must happen as a 32-bit write.
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* This does not (yet) support writing individual bytes
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*/
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if (value == ~0)
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bar->which = 1;
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else {
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u32 tmpval;
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pci_read_config_dword(dev, offset, &tmpval);
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if (tmpval != bar->val && value == bar->val) {
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/* Allow restoration of bar value. */
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pci_write_config_dword(dev, offset, bar->val);
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}
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bar->which = 0;
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}
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return 0;
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}
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static int bar_read(struct pci_dev *dev, int offset, u32 * value, void *data)
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{
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struct pci_bar_info *bar = data;
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if (unlikely(!bar)) {
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printk(KERN_WARNING "pciback: driver data not found for %s\n",
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pci_name(dev));
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return XEN_PCI_ERR_op_failed;
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}
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*value = bar->which ? bar->len_val : bar->val;
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return 0;
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}
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static inline void read_dev_bar(struct pci_dev *dev,
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struct pci_bar_info *bar_info, int offset,
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u32 len_mask)
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{
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int pos;
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struct resource *res = dev->resource;
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if (offset == PCI_ROM_ADDRESS || offset == PCI_ROM_ADDRESS1)
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pos = PCI_ROM_RESOURCE;
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else {
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pos = (offset - PCI_BASE_ADDRESS_0) / 4;
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if (pos && ((res[pos - 1].flags & (PCI_BASE_ADDRESS_SPACE |
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PCI_BASE_ADDRESS_MEM_TYPE_MASK)) ==
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(PCI_BASE_ADDRESS_SPACE_MEMORY |
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PCI_BASE_ADDRESS_MEM_TYPE_64))) {
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bar_info->val = res[pos - 1].start >> 32;
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bar_info->len_val = res[pos - 1].end >> 32;
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return;
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}
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}
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bar_info->val = res[pos].start |
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(res[pos].flags & PCI_REGION_FLAG_MASK);
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bar_info->len_val = res[pos].end - res[pos].start + 1;
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}
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static void *bar_init(struct pci_dev *dev, int offset)
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{
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struct pci_bar_info *bar = kmalloc(sizeof(*bar), GFP_KERNEL);
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if (!bar)
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return ERR_PTR(-ENOMEM);
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read_dev_bar(dev, bar, offset, ~0);
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bar->which = 0;
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return bar;
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}
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static void *rom_init(struct pci_dev *dev, int offset)
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{
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struct pci_bar_info *bar = kmalloc(sizeof(*bar), GFP_KERNEL);
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if (!bar)
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return ERR_PTR(-ENOMEM);
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read_dev_bar(dev, bar, offset, ~PCI_ROM_ADDRESS_ENABLE);
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bar->which = 0;
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return bar;
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}
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static void bar_reset(struct pci_dev *dev, int offset, void *data)
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{
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struct pci_bar_info *bar = data;
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bar->which = 0;
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}
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static void bar_release(struct pci_dev *dev, int offset, void *data)
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{
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kfree(data);
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}
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static int pciback_read_vendor(struct pci_dev *dev, int offset,
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u16 *value, void *data)
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{
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*value = dev->vendor;
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return 0;
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}
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static int pciback_read_device(struct pci_dev *dev, int offset,
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u16 *value, void *data)
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{
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*value = dev->device;
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return 0;
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}
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static int interrupt_read(struct pci_dev *dev, int offset, u8 * value,
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void *data)
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{
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*value = (u8) dev->irq;
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return 0;
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}
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static int bist_write(struct pci_dev *dev, int offset, u8 value, void *data)
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{
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u8 cur_value;
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int err;
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err = pci_read_config_byte(dev, offset, &cur_value);
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if (err)
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goto out;
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if ((cur_value & ~PCI_BIST_START) == (value & ~PCI_BIST_START)
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|| value == PCI_BIST_START)
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err = pci_write_config_byte(dev, offset, value);
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out:
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return err;
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}
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static const struct config_field header_common[] = {
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{
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.offset = PCI_VENDOR_ID,
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.size = 2,
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.u.w.read = pciback_read_vendor,
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},
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{
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.offset = PCI_DEVICE_ID,
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.size = 2,
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.u.w.read = pciback_read_device,
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},
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{
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.offset = PCI_COMMAND,
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.size = 2,
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.u.w.read = command_read,
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.u.w.write = command_write,
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},
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{
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.offset = PCI_INTERRUPT_LINE,
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.size = 1,
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.u.b.read = interrupt_read,
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},
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{
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.offset = PCI_INTERRUPT_PIN,
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.size = 1,
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.u.b.read = pciback_read_config_byte,
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},
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{
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/* Any side effects of letting driver domain control cache line? */
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.offset = PCI_CACHE_LINE_SIZE,
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.size = 1,
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.u.b.read = pciback_read_config_byte,
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.u.b.write = pciback_write_config_byte,
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},
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{
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.offset = PCI_LATENCY_TIMER,
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.size = 1,
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.u.b.read = pciback_read_config_byte,
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},
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{
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.offset = PCI_BIST,
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.size = 1,
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.u.b.read = pciback_read_config_byte,
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.u.b.write = bist_write,
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},
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{}
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};
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#define CFG_FIELD_BAR(reg_offset) \
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{ \
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.offset = reg_offset, \
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.size = 4, \
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.init = bar_init, \
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.reset = bar_reset, \
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.release = bar_release, \
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.u.dw.read = bar_read, \
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.u.dw.write = bar_write, \
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}
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#define CFG_FIELD_ROM(reg_offset) \
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{ \
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.offset = reg_offset, \
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.size = 4, \
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.init = rom_init, \
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.reset = bar_reset, \
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.release = bar_release, \
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.u.dw.read = bar_read, \
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.u.dw.write = rom_write, \
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}
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static const struct config_field header_0[] = {
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CFG_FIELD_BAR(PCI_BASE_ADDRESS_0),
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CFG_FIELD_BAR(PCI_BASE_ADDRESS_1),
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CFG_FIELD_BAR(PCI_BASE_ADDRESS_2),
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CFG_FIELD_BAR(PCI_BASE_ADDRESS_3),
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CFG_FIELD_BAR(PCI_BASE_ADDRESS_4),
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CFG_FIELD_BAR(PCI_BASE_ADDRESS_5),
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CFG_FIELD_ROM(PCI_ROM_ADDRESS),
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{}
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};
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static const struct config_field header_1[] = {
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CFG_FIELD_BAR(PCI_BASE_ADDRESS_0),
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CFG_FIELD_BAR(PCI_BASE_ADDRESS_1),
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CFG_FIELD_ROM(PCI_ROM_ADDRESS1),
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{}
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};
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int pciback_config_header_add_fields(struct pci_dev *dev)
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{
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int err;
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err = pciback_config_add_fields(dev, header_common);
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if (err)
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goto out;
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switch (dev->hdr_type) {
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case PCI_HEADER_TYPE_NORMAL:
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err = pciback_config_add_fields(dev, header_0);
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break;
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case PCI_HEADER_TYPE_BRIDGE:
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err = pciback_config_add_fields(dev, header_1);
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break;
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default:
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err = -EINVAL;
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printk(KERN_ERR "pciback: %s: Unsupported header type %d!\n",
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pci_name(dev), dev->hdr_type);
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break;
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}
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out:
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return err;
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}
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