zhangqing 0bbe62eb92 clk: rockchip: rk3368: enable the CLK_SET_RATE_PARENT flag for spdif_8ch ... SPDIF_8CH set freq need to select parent and calculate parent freq. so just mark it as the CLK_SET_RATE_PARENT flag. Signed-off-by: zhangqing <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>		2016-01-25 11:04:51 +01:00
..
clk-cpu.c	clk: rockchip: allow more than 2 parents for cpuclk	2015-12-09 22:30:42 +01:00
clk-inverter.c	clk: Convert __clk_get_name(hw->clk) to clk_hw_get_name(hw)	2015-08-24 16:49:12 -07:00
clk-mmc-phase.c	The majority of the changes are driver updates and new device	2015-11-05 12:59:36 -08:00
clk-pll.c	clk: rockchip: add new pll-type for rk3036 and similar socs	2015-11-23 21:55:07 +01:00
clk-rk3036.c	clk: rockchip: rk3036: enable the CLK_IGNORE_UNUSED flag for hclk_vio_bus	2016-01-24 23:29:16 +01:00
clk-rk3188.c	Merge branch 'clk-rockchip' into clk-next	2016-01-02 13:41:09 -08:00
clk-rk3228.c	clk: rockchip: only enter pll slow-mode directly before reboots on rk3288	2015-12-21 02:01:19 +01:00
clk-rk3288.c	Merge branch 'clk-rockchip' into clk-next	2016-01-02 13:41:09 -08:00
clk-rk3368.c	clk: rockchip: rk3368: enable the CLK_SET_RATE_PARENT flag for spdif_8ch	2016-01-25 11:04:51 +01:00
clk-rockchip.c
clk.c	Merge branch 'clk-rockchip' into clk-next	2015-12-23 13:08:56 -08:00
clk.h	Merge branch 'clk-rockchip' into clk-next	2016-01-02 13:41:09 -08:00
Makefile	clk: rockchip: add clock controller for rk3228	2015-12-12 20:04:54 +01:00
softrst.c	clk: rockchip: add reset controller	2014-07-13 12:17:07 -07:00