130f1b8f35
Add standard #defines for the Supported Link Speeds field in the PCIe
Link Capabilities register.
Note that prior to PCIe spec r3.0, these encodings were defined:
0001b 2.5GT/s Link speed supported
0010b 5.0GT/s and 2.5GT/s Link speed supported
Starting with spec r3.0, these encodings refer to bits 0 and 1 in the
Supported Link Speeds Vector in the Link Capabilities 2 register, and bits
0 and 1 there mean 2.5 GT/s and 5.0 GT/s, respectively. Therefore, code
that followed r2.0 and interpreted 0x1 as 2.5GT/s and 0x2 as 5.0GT/s will
continue to work, and we can identify a device using the new encodings
because it will have a non-zero Link Capabilities 2 register.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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| clocksource | ||
| crypto | ||
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| linux | ||
| math-emu | ||
| media | ||
| memory | ||
| misc | ||
| net | ||
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| ras | ||
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| rxrpc | ||
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| sound | ||
| target | ||
| trace | ||
| uapi | ||
| video | ||
| xen | ||
| Kbuild | ||