1c3d038bd5
soc_common already initializes state.wrprot to zero, so explicitly setting wrprot to zero in the socket drivers has no additional effect. Acked-by: Dominik Brodowski <linux@dominikbrodowski.net> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
133 lines
3 KiB
C
133 lines
3 KiB
C
/*
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* drivers/pcmcia/sa1100_nanoengine.c
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*
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* PCMCIA implementation routines for BSI nanoEngine.
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*
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* In order to have a fully functional pcmcia subsystem in a BSE nanoEngine
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* board you should carefully read this:
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* http://cambuca.ldhs.cetuc.puc-rio.br/nanoengine/
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*
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* Copyright (C) 2010 Marcelo Roberto Jimenez <mroberto@cpti.cetuc.puc-rio.br>
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*
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* Based on original work for kernel 2.4 by
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* Miguel Freitas <miguel@cpti.cetuc.puc-rio.br>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/device.h>
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#include <linux/errno.h>
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#include <linux/gpio.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/signal.h>
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#include <asm/mach-types.h>
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#include <asm/irq.h>
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#include <mach/hardware.h>
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#include <mach/nanoengine.h>
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#include "sa1100_generic.h"
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struct nanoengine_pins {
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unsigned output_pins;
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unsigned clear_outputs;
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int gpio_rst;
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int gpio_cd;
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int gpio_rdy;
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};
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static struct nanoengine_pins nano_skts[] = {
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{
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.gpio_rst = GPIO_PC_RESET0,
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.gpio_cd = GPIO_PC_CD0,
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.gpio_rdy = GPIO_PC_READY0,
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}, {
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.gpio_rst = GPIO_PC_RESET1,
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.gpio_cd = GPIO_PC_CD1,
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.gpio_rdy = GPIO_PC_READY1,
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}
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};
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unsigned num_nano_pcmcia_sockets = ARRAY_SIZE(nano_skts);
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static int nanoengine_pcmcia_hw_init(struct soc_pcmcia_socket *skt)
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{
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unsigned i = skt->nr;
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int ret;
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if (i >= num_nano_pcmcia_sockets)
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return -ENXIO;
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ret = gpio_request_one(nano_skts[i].gpio_rst, GPIOF_OUT_INIT_LOW,
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i ? "PC RST1" : "PC RST0");
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if (ret)
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return ret;
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skt->stat[SOC_STAT_CD].gpio = nano_skts[i].gpio_cd;
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skt->stat[SOC_STAT_CD].name = i ? "PC CD1" : "PC CD0";
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skt->stat[SOC_STAT_RDY].gpio = nano_skts[i].gpio_rdy;
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skt->stat[SOC_STAT_RDY].name = i ? "PC RDY1" : "PC RDY0";
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return 0;
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}
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static void nanoengine_pcmcia_hw_shutdown(struct soc_pcmcia_socket *skt)
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{
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gpio_free(nano_skts[skt->nr].gpio_rst);
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}
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static int nanoengine_pcmcia_configure_socket(
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struct soc_pcmcia_socket *skt, const socket_state_t *state)
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{
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unsigned i = skt->nr;
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if (i >= num_nano_pcmcia_sockets)
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return -ENXIO;
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gpio_set_value(nano_skts[skt->nr].gpio_rst, !!(state->flags & SS_RESET));
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return 0;
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}
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static void nanoengine_pcmcia_socket_state(
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struct soc_pcmcia_socket *skt, struct pcmcia_state *state)
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{
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unsigned i = skt->nr;
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if (i >= num_nano_pcmcia_sockets)
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return;
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state->bvd1 = 1;
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state->bvd2 = 1;
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state->vs_3v = 1; /* Can only apply 3.3V */
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state->vs_Xv = 0;
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}
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static struct pcmcia_low_level nanoengine_pcmcia_ops = {
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.owner = THIS_MODULE,
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.hw_init = nanoengine_pcmcia_hw_init,
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.hw_shutdown = nanoengine_pcmcia_hw_shutdown,
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.configure_socket = nanoengine_pcmcia_configure_socket,
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.socket_state = nanoengine_pcmcia_socket_state,
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};
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int pcmcia_nanoengine_init(struct device *dev)
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{
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int ret = -ENODEV;
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if (machine_is_nanoengine())
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ret = sa11xx_drv_pcmcia_probe(
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dev, &nanoengine_pcmcia_ops, 0, 2);
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return ret;
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}
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