1a748d2bc5
This patch adds new at91 pll clock implementation using common clk framework. The pll clock layout describe the PLLX register layout. There are four pll clock layouts: - at91rm9200 - at91sam9g20 - at91sam9g45 - sama5d3 PLL clocks are given characteristics: - min/max clock source rate - ranges of valid clock output rates - values to set in out and icpll fields for each supported output range These characteristics are checked during rate change to avoid over/underclocking. These characteristics are described in atmel's SoC datasheet in "Electrical Characteristics" paragraph. Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
75 lines
1.9 KiB
C
75 lines
1.9 KiB
C
/*
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* drivers/clk/at91/pmc.h
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*
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* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef __PMC_H_
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#define __PMC_H_
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#include <linux/io.h>
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#include <linux/irqdomain.h>
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#include <linux/spinlock.h>
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struct clk_range {
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unsigned long min;
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unsigned long max;
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};
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#define CLK_RANGE(MIN, MAX) {.min = MIN, .max = MAX,}
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struct at91_pmc_caps {
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u32 available_irqs;
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};
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struct at91_pmc {
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void __iomem *regbase;
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int virq;
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spinlock_t lock;
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const struct at91_pmc_caps *caps;
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struct irq_domain *irqdomain;
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};
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static inline void pmc_lock(struct at91_pmc *pmc)
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{
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spin_lock(&pmc->lock);
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}
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static inline void pmc_unlock(struct at91_pmc *pmc)
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{
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spin_unlock(&pmc->lock);
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}
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static inline u32 pmc_read(struct at91_pmc *pmc, int offset)
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{
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return readl(pmc->regbase + offset);
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}
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static inline void pmc_write(struct at91_pmc *pmc, int offset, u32 value)
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{
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writel(value, pmc->regbase + offset);
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}
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int of_at91_get_clk_range(struct device_node *np, const char *propname,
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struct clk_range *range);
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extern void __init of_at91rm9200_clk_main_setup(struct device_node *np,
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struct at91_pmc *pmc);
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extern void __init of_at91rm9200_clk_pll_setup(struct device_node *np,
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struct at91_pmc *pmc);
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extern void __init of_at91sam9g45_clk_pll_setup(struct device_node *np,
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struct at91_pmc *pmc);
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extern void __init of_at91sam9g20_clk_pllb_setup(struct device_node *np,
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struct at91_pmc *pmc);
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extern void __init of_sama5d3_clk_pll_setup(struct device_node *np,
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struct at91_pmc *pmc);
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extern void __init of_at91sam9x5_clk_plldiv_setup(struct device_node *np,
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struct at91_pmc *pmc);
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#endif /* __PMC_H_ */
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