linux-hardened/include/linux/clk
Boris BREZILLON 1a748d2bc5 clk: at91: add PMC pll clocks
This patch adds new at91 pll clock implementation using common clk framework.

The pll clock layout describe the PLLX register layout.
There are four pll clock layouts:
- at91rm9200
- at91sam9g20
- at91sam9g45
- sama5d3

PLL clocks are given characteristics:
- min/max clock source rate
- ranges of valid clock output rates
- values to set in out and icpll fields for each supported output range

These characteristics are checked during rate change to avoid
over/underclocking.

These characteristics are described in atmel's SoC datasheet in
"Electrical Characteristics" paragraph.

Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2013-12-02 15:31:22 +01:00
..
at91_pmc.h clk: at91: add PMC pll clocks 2013-12-02 15:31:22 +01:00
bcm2835.h
mxs.h ARM: mxs: remove custom .init_time hook 2013-09-29 21:09:34 +02:00
tegra.h clk: tegra: fix ifdef for tegra_periph_reset_assert inline 2013-06-24 14:17:59 -07:00
zynq.h arm: zynq: Migrate platform to clock controller 2013-05-27 09:21:22 +02:00