ca148125e6
Power throttling make deterministic delay loops impossible. Re-implement delays using the cycle counter. This also allows us to get rid of the code that calculates loops per jiffy. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1317/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
137 lines
3 KiB
C
137 lines
3 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2007 by Ralf Baechle
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*/
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#include <linux/clocksource.h>
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#include <linux/init.h>
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#include <asm/time.h>
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#include <asm/octeon/octeon.h>
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#include <asm/octeon/cvmx-ipd-defs.h>
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/*
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* Set the current core's cvmcount counter to the value of the
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* IPD_CLK_COUNT. We do this on all cores as they are brought
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* on-line. This allows for a read from a local cpu register to
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* access a synchronized counter.
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*
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*/
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void octeon_init_cvmcount(void)
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{
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unsigned long flags;
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unsigned loops = 2;
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/* Clobber loops so GCC will not unroll the following while loop. */
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asm("" : "+r" (loops));
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local_irq_save(flags);
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/*
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* Loop several times so we are executing from the cache,
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* which should give more deterministic timing.
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*/
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while (loops--)
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write_c0_cvmcount(cvmx_read_csr(CVMX_IPD_CLK_COUNT));
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local_irq_restore(flags);
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}
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static cycle_t octeon_cvmcount_read(struct clocksource *cs)
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{
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return read_c0_cvmcount();
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}
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static struct clocksource clocksource_mips = {
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.name = "OCTEON_CVMCOUNT",
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.read = octeon_cvmcount_read,
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.mask = CLOCKSOURCE_MASK(64),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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unsigned long long notrace sched_clock(void)
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{
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/* 64-bit arithmatic can overflow, so use 128-bit. */
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u64 t1, t2, t3;
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unsigned long long rv;
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u64 mult = clocksource_mips.mult;
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u64 shift = clocksource_mips.shift;
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u64 cnt = read_c0_cvmcount();
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asm (
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"dmultu\t%[cnt],%[mult]\n\t"
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"nor\t%[t1],$0,%[shift]\n\t"
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"mfhi\t%[t2]\n\t"
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"mflo\t%[t3]\n\t"
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"dsll\t%[t2],%[t2],1\n\t"
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"dsrlv\t%[rv],%[t3],%[shift]\n\t"
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"dsllv\t%[t1],%[t2],%[t1]\n\t"
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"or\t%[rv],%[t1],%[rv]\n\t"
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: [rv] "=&r" (rv), [t1] "=&r" (t1), [t2] "=&r" (t2), [t3] "=&r" (t3)
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: [cnt] "r" (cnt), [mult] "r" (mult), [shift] "r" (shift)
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: "hi", "lo");
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return rv;
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}
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void __init plat_time_init(void)
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{
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clocksource_mips.rating = 300;
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clocksource_set_clock(&clocksource_mips, mips_hpt_frequency);
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clocksource_register(&clocksource_mips);
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}
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static u64 octeon_udelay_factor;
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static u64 octeon_ndelay_factor;
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void __init octeon_setup_delays(void)
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{
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octeon_udelay_factor = octeon_get_clock_rate() / 1000000;
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/*
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* For __ndelay we divide by 2^16, so the factor is multiplied
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* by the same amount.
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*/
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octeon_ndelay_factor = (octeon_udelay_factor * 0x10000ull) / 1000ull;
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preset_lpj = octeon_get_clock_rate() / HZ;
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}
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void __udelay(unsigned long us)
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{
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u64 cur, end, inc;
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cur = read_c0_cvmcount();
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inc = us * octeon_udelay_factor;
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end = cur + inc;
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while (end > cur)
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cur = read_c0_cvmcount();
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}
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EXPORT_SYMBOL(__udelay);
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void __ndelay(unsigned long ns)
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{
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u64 cur, end, inc;
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cur = read_c0_cvmcount();
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inc = ((ns * octeon_ndelay_factor) >> 16);
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end = cur + inc;
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while (end > cur)
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cur = read_c0_cvmcount();
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}
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EXPORT_SYMBOL(__ndelay);
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void __delay(unsigned long loops)
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{
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u64 cur, end;
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cur = read_c0_cvmcount();
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end = cur + loops;
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while (end > cur)
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cur = read_c0_cvmcount();
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}
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EXPORT_SYMBOL(__delay);
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