89b831ef8b
MC4_MISC - DRAM Errors Threshold Register realized under AMD K8 Rev F. This register is used to count correctable and uncorrectable ECC errors that occur during DRAM read operations. The user may interface through sysfs files in order to change the threshold configuration. bank%d/error_count - reads current error count, write to clear. bank%d/interrupt_enable - set/clear interrupt enable. bank%d/threshold_limit - read/write the threshold limit. APIC vector 0xF9 in hw_irq.h. 5 software defined bank ids in mce.h. new apic.c function to setup threshold apic lvt. defaults to interrupt off, count enabled, and threshold limit max. sysfs interface created on /sys/devices/system/threshold. AK: added some ifdefs to make it compile on UP Signed-off-by: Jacob Shin <jacob.shin@amd.com> Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
90 lines
2.4 KiB
C
90 lines
2.4 KiB
C
#ifndef _ASM_MCE_H
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#define _ASM_MCE_H 1
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#include <asm/ioctls.h>
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#include <asm/types.h>
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/*
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* Machine Check support for x86
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*/
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#define MCG_CTL_P (1UL<<8) /* MCG_CAP register available */
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#define MCG_STATUS_RIPV (1UL<<0) /* restart ip valid */
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#define MCG_STATUS_EIPV (1UL<<1) /* eip points to correct instruction */
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#define MCG_STATUS_MCIP (1UL<<2) /* machine check in progress */
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#define MCI_STATUS_VAL (1UL<<63) /* valid error */
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#define MCI_STATUS_OVER (1UL<<62) /* previous errors lost */
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#define MCI_STATUS_UC (1UL<<61) /* uncorrected error */
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#define MCI_STATUS_EN (1UL<<60) /* error enabled */
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#define MCI_STATUS_MISCV (1UL<<59) /* misc error reg. valid */
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#define MCI_STATUS_ADDRV (1UL<<58) /* addr reg. valid */
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#define MCI_STATUS_PCC (1UL<<57) /* processor context corrupt */
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/* Fields are zero when not available */
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struct mce {
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__u64 status;
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__u64 misc;
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__u64 addr;
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__u64 mcgstatus;
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__u64 rip;
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__u64 tsc; /* cpu time stamp counter */
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__u64 res1; /* for future extension */
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__u64 res2; /* dito. */
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__u8 cs; /* code segment */
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__u8 bank; /* machine check bank */
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__u8 cpu; /* cpu that raised the error */
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__u8 finished; /* entry is valid */
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__u32 pad;
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};
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/*
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* This structure contains all data related to the MCE log.
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* Also carries a signature to make it easier to find from external debugging tools.
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* Each entry is only valid when its finished flag is set.
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*/
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#define MCE_LOG_LEN 32
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struct mce_log {
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char signature[12]; /* "MACHINECHECK" */
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unsigned len; /* = MCE_LOG_LEN */
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unsigned next;
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unsigned flags;
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unsigned pad0;
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struct mce entry[MCE_LOG_LEN];
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};
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#define MCE_OVERFLOW 0 /* bit 0 in flags means overflow */
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#define MCE_LOG_SIGNATURE "MACHINECHECK"
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#define MCE_GET_RECORD_LEN _IOR('M', 1, int)
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#define MCE_GET_LOG_LEN _IOR('M', 2, int)
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#define MCE_GETCLEAR_FLAGS _IOR('M', 3, int)
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/* Software defined banks */
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#define MCE_EXTENDED_BANK 128
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#define MCE_THERMAL_BANK MCE_EXTENDED_BANK + 0
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#define MCE_THRESHOLD_BASE MCE_EXTENDED_BANK + 1 /* MCE_AMD */
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#define MCE_THRESHOLD_DRAM_ECC MCE_THRESHOLD_BASE + 4
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void mce_log(struct mce *m);
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#ifdef CONFIG_X86_MCE_INTEL
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void mce_intel_feature_init(struct cpuinfo_x86 *c);
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#else
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static inline void mce_intel_feature_init(struct cpuinfo_x86 *c)
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{
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}
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#endif
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#ifdef CONFIG_X86_MCE_AMD
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void mce_amd_feature_init(struct cpuinfo_x86 *c);
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#else
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static inline void mce_amd_feature_init(struct cpuinfo_x86 *c)
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{
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}
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#endif
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#endif
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