6171de8f57
The AT91RM9200 system header file (at91rm9200_sys.h) has been split into separate header files for each peripheral. This was necessary since some of the system peripherals are also used on AT91SAM9260 and AT91SAM9261. The new SAM9-specific register bits have also been defined. Signed-off-by: Andrew Victor <andrew@sanpeople.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
45 lines
2.1 KiB
C
45 lines
2.1 KiB
C
/*
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* include/asm-arm/arch-at91rm9200/at91_dbgu.h
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*
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* Copyright (C) 2005 Ivan Kokshaysky
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* Copyright (C) SAN People
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*
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* Debug Unit (DBGU) - System peripherals registers.
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* Based on AT91RM9200 datasheet revision E.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef AT91_DBGU_H
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#define AT91_DBGU_H
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#define AT91_DBGU_CR (AT91_DBGU + 0x00) /* Control Register */
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#define AT91_DBGU_MR (AT91_DBGU + 0x04) /* Mode Register */
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#define AT91_DBGU_IER (AT91_DBGU + 0x08) /* Interrupt Enable Register */
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#define AT91_DBGU_TXRDY (1 << 1) /* Transmitter Ready */
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#define AT91_DBGU_TXEMPTY (1 << 9) /* Transmitter Empty */
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#define AT91_DBGU_IDR (AT91_DBGU + 0x0c) /* Interrupt Disable Register */
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#define AT91_DBGU_IMR (AT91_DBGU + 0x10) /* Interrupt Mask Register */
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#define AT91_DBGU_SR (AT91_DBGU + 0x14) /* Status Register */
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#define AT91_DBGU_RHR (AT91_DBGU + 0x18) /* Receiver Holding Register */
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#define AT91_DBGU_THR (AT91_DBGU + 0x1c) /* Transmitter Holding Register */
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#define AT91_DBGU_BRGR (AT91_DBGU + 0x20) /* Baud Rate Generator Register */
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#define AT91_DBGU_CIDR (AT91_DBGU + 0x40) /* Chip ID Register */
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#define AT91_DBGU_EXID (AT91_DBGU + 0x44) /* Chip ID Extension Register */
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#define AT91_CIDR_VERSION (0x1f << 0) /* Version of the Device */
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#define AT91_CIDR_EPROC (7 << 5) /* Embedded Processor */
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#define AT91_CIDR_NVPSIZ (0xf << 8) /* Nonvolatile Program Memory Size */
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#define AT91_CIDR_NVPSIZ2 (0xf << 12) /* Second Nonvolatile Program Memory Size */
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#define AT91_CIDR_SRAMSIZ (0xf << 16) /* Internal SRAM Size */
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#define AT91_CIDR_ARCH (0xff << 20) /* Architecture Identifier */
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#define AT91_CIDR_NVPTYP (7 << 28) /* Nonvolatile Program Memory Type */
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#define AT91_CIDR_EXT (1 << 31) /* Extension Flag */
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#define AT91_DBGU_FNR (AT91_DBGU + 0x48) /* Force NTRST Register [SAM9 only] */
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#define AT91_DBGU_FNTRST (1 << 0) /* Force NTRST */
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#endif
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