12458ea06e
This patch adds new version of the PPC440SPe ADMA driver. Signed-off-by: Yuri Tikhonov <yur@emcraft.com> Signed-off-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
110 lines
3.5 KiB
C
110 lines
3.5 KiB
C
/*
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* 440SPe's XOR engines support header file
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*
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* 2006-2009 (C) DENX Software Engineering.
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*
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* Author: Yuri Tikhonov <yur@emcraft.com>
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*
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* This file is licensed under the term of the GNU General Public License
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* version 2. The program licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#ifndef _PPC440SPE_XOR_H
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#define _PPC440SPE_XOR_H
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#include <linux/types.h>
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/* Number of XOR engines available on the contoller */
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#define XOR_ENGINES_NUM 1
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/* Number of operands supported in the h/w */
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#define XOR_MAX_OPS 16
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/*
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* XOR Command Block Control Register bits
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*/
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#define XOR_CBCR_LNK_BIT (1<<31) /* link present */
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#define XOR_CBCR_TGT_BIT (1<<30) /* target present */
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#define XOR_CBCR_CBCE_BIT (1<<29) /* command block compete enable */
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#define XOR_CBCR_RNZE_BIT (1<<28) /* result not zero enable */
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#define XOR_CBCR_XNOR_BIT (1<<15) /* XOR/XNOR */
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#define XOR_CDCR_OAC_MSK (0x7F) /* operand address count */
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/*
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* XORCore Status Register bits
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*/
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#define XOR_SR_XCP_BIT (1<<31) /* core processing */
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#define XOR_SR_ICB_BIT (1<<17) /* invalid CB */
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#define XOR_SR_IC_BIT (1<<16) /* invalid command */
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#define XOR_SR_IPE_BIT (1<<15) /* internal parity error */
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#define XOR_SR_RNZ_BIT (1<<2) /* result not Zero */
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#define XOR_SR_CBC_BIT (1<<1) /* CB complete */
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#define XOR_SR_CBLC_BIT (1<<0) /* CB list complete */
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/*
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* XORCore Control Set and Reset Register bits
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*/
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#define XOR_CRSR_XASR_BIT (1<<31) /* soft reset */
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#define XOR_CRSR_XAE_BIT (1<<30) /* enable */
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#define XOR_CRSR_RCBE_BIT (1<<29) /* refetch CB enable */
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#define XOR_CRSR_PAUS_BIT (1<<28) /* pause */
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#define XOR_CRSR_64BA_BIT (1<<27) /* 64/32 CB format */
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#define XOR_CRSR_CLP_BIT (1<<25) /* continue list processing */
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/*
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* XORCore Interrupt Enable Register
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*/
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#define XOR_IE_ICBIE_BIT (1<<17) /* Invalid Command Block IRQ Enable */
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#define XOR_IE_ICIE_BIT (1<<16) /* Invalid Command IRQ Enable */
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#define XOR_IE_RPTIE_BIT (1<<14) /* Read PLB Timeout Error IRQ Enable */
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#define XOR_IE_CBCIE_BIT (1<<1) /* CB complete interrupt enable */
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#define XOR_IE_CBLCI_BIT (1<<0) /* CB list complete interrupt enable */
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/*
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* XOR Accelerator engine Command Block Type
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*/
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struct xor_cb {
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/*
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* Basic 64-bit format XOR CB (Table 19-1, p.463, 440spe_um_1_22.pdf)
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*/
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u32 cbc; /* control */
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u32 cbbc; /* byte count */
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u32 cbs; /* status */
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u8 pad0[4]; /* reserved */
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u32 cbtah; /* target address high */
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u32 cbtal; /* target address low */
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u32 cblah; /* link address high */
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u32 cblal; /* link address low */
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struct {
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u32 h;
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u32 l;
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} __attribute__ ((packed)) ops[16];
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} __attribute__ ((packed));
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/*
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* XOR hardware registers Table 19-3, UM 1.22
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*/
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struct xor_regs {
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u32 op_ar[16][2]; /* operand address[0]-high,[1]-low registers */
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u8 pad0[352]; /* reserved */
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u32 cbcr; /* CB control register */
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u32 cbbcr; /* CB byte count register */
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u32 cbsr; /* CB status register */
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u8 pad1[4]; /* reserved */
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u32 cbtahr; /* operand target address high register */
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u32 cbtalr; /* operand target address low register */
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u32 cblahr; /* CB link address high register */
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u32 cblalr; /* CB link address low register */
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u32 crsr; /* control set register */
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u32 crrr; /* control reset register */
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u32 ccbahr; /* current CB address high register */
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u32 ccbalr; /* current CB address low register */
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u32 plbr; /* PLB configuration register */
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u32 ier; /* interrupt enable register */
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u32 pecr; /* parity error count register */
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u32 sr; /* status register */
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u32 revidr; /* revision ID register */
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};
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#endif /* _PPC440SPE_XOR_H */
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