a09e64fbc0
This just leaves include/asm-arm/plat-* to deal with. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
37 lines
1 KiB
ArmAsm
37 lines
1 KiB
ArmAsm
/*
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* arch/arm/mach-iop33x/include/mach/entry-macro.S
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*
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* Low-level IRQ helper macros for IOP33x-based platforms
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <mach/iop33x.h>
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.macro disable_fiq
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.endm
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.macro get_irqnr_preamble, base, tmp
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mrc p15, 0, \tmp, c15, c1, 0
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orr \tmp, \tmp, #(1 << 6)
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mcr p15, 0, \tmp, c15, c1, 0 @ Enable cp6 access
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mrc p15, 0, \tmp, c15, c1, 0
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mov \tmp, \tmp
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sub pc, pc, #4 @ cp_wait
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.endm
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.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
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mrc p6, 0, \irqstat, c14, c0, 0 @ Read IINTVEC
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cmp \irqstat, #0
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mrceq p6, 0, \irqstat, c14, c0, 0 @ erratum 63 workaround
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adds \irqnr, \irqstat, #1
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movne \irqnr, \irqstat, lsr #2
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.endm
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.macro arch_ret_to_user, tmp1, tmp2
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mrc p15, 0, \tmp1, c15, c1, 0
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ands \tmp2, \tmp1, #(1 << 6)
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bicne \tmp1, \tmp1, #(1 << 6)
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mcrne p15, 0, \tmp1, c15, c1, 0 @ Disable cp6 access
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.endm
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